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Proceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005.

11-14 Dec. 2005

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  • Proceedings 2005 IEEE International Conference on Field Programmable Technology

    Publication Year: 2005, Page(s): i
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  • Copyright page

    Publication Year: 2005, Page(s): ii
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  • Table of contents

    Publication Year: 2005, Page(s):iii - vi
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  • Message from the General Chair

    Publication Year: 2005, Page(s): vii
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  • Message From the Technical Program Chair

    Publication Year: 2005, Page(s): viii
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  • Organizing Committee

    Publication Year: 2005, Page(s): ix
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  • Technical Program Committee

    Publication Year: 2005, Page(s): x
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  • [Breaker page]

    Publication Year: 2005, Page(s): xii
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  • [Breaker page]

    Publication Year: 2005, Page(s):xiii - xiv
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  • Additional reviewers

    Publication Year: 2005, Page(s): xi
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  • Platform-based synthesis for field-programmable SOCs

    Publication Year: 2005, Page(s): xv
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  • Low power and high speed issues in FPGA chips

    Publication Year: 2005, Page(s): xvi
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  • [Breaker page]

    Publication Year: 2005, Page(s):xvii - xviii
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  • System architectures and design patterns for reconfigurable computing

    Publication Year: 2005, Page(s):xvix - xviy
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  • Reconfigurable hardware operating systems

    Publication Year: 2005, Page(s): xxi
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  • [Breaker page]

    Publication Year: 2005, Page(s): xxii
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  • [Breaker page]

    Publication Year: 2005, Page(s):1 - 2
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  • [Breaker page]

    Publication Year: 2005, Page(s):3 - 4
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  • A custom instruction approach for hardware and software implementations of finite field arithmetic over F2163 using Gaussian normal bases

    Publication Year: 2005, Page(s):5 - 12
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (236 KB) | HTML iconHTML

    In this paper we explore the potential use of custom instructions in a reconfigurable hardware platform to accelerate arithmetic operations in the binary field F2163 using a Gaussian normal basis representation. System-on-chip (SOC) techniques based on field programmable gate arrays (FPGAs) are used, making it possible to run real applications on the system while considering all executi... View full abstract»

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  • High-radix systolic modular multiplication on reconfigurable hardware

    Publication Year: 2005, Page(s):13 - 18
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (131 KB) | HTML iconHTML

    The overall aim of the work presented in this paper has been to develop Montgomery modular multiplication architectures suitable for implementation on modern reconfigurable hardware. Accordingly, novel high radix systolic array Montgomery multiplier designs are presented, as we believe that the inherent regular structure and absence of global interconnect associated with these, make them well-suit... View full abstract»

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  • Pipelining saturated accumulation

    Publication Year: 2005, Page(s):19 - 26
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (199 KB) | HTML iconHTML

    Aggressive pipelining allows FPGAs to achieve high throughput on many digital signal processing applications. However, cyclic data dependencies in the computation can limit pipelining and reduce the efficiency and speed of an FPGA implementation. Saturated accumulation is an important example where such a cycle limits the throughput of signal processing applications. We show how to reformulate sat... View full abstract»

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  • A parameterized floating-point exponential function for FPGAs

    Publication Year: 2005, Page(s):27 - 34
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (197 KB) | HTML iconHTML

    A parameterized floating point exponential operator is presented. In single precision, it uses a small fraction of the FPGA's resources and has a smaller latency than its software equivalent on a high-end processor, and ten times the throughput in pipelined version. Previous work had shown that FPGAs could use massive parallelism to balance the poor performance of their basic floating-point operat... View full abstract»

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  • [Breaker page]

    Publication Year: 2005, Page(s):35 - 36
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  • The Erlangen slot machine: increasing flexibility in FPGA-based reconfigurable platforms

    Publication Year: 2005, Page(s):37 - 42
    Cited by:  Papers (25)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (459 KB) | HTML iconHTML

    We present a new concept as well as the implementation of an FPGA based reconfigurable platform, the Erlangen slot machine (ESM). One main advantage of this platform is the possibility for each module to access its periphery independent from its location through a programmable crossbar, allowing an unrestricted relocation of modules on the device. Furthermore, we propose different intermodule comm... View full abstract»

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  • Task placement for heterogeneous reconfigurable architectures

    Publication Year: 2005, Page(s):43 - 50
    Cited by:  Papers (19)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (617 KB) | HTML iconHTML

    The concept of partial reconfiguration offers the possibility to dynamically place and remove hardware tasks on reconfigurable architectures, like FPGAs. Common placement algorithms, e.g. Best Fit, are designed for homogeneous architectures, since they do not consider any placement constraints of the hardware tasks. Due to the integration of, e.g., dedicated memory, current FPGAs are heterogeneous... View full abstract»

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