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Digital System Design, 2005. Proceedings. 8th Euromicro Conference on

Date Aug. 30 2005-Sept. 3 2005

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  • Proceedings. 8th Euromicro Conference on Digital System Design

    Publication Year: 2005
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  • 8th Euromicro Conference on Digital System Design - Title Page

    Publication Year: 2005 , Page(s): i - iii
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  • 8th Euromicro Conference on Digital System Design - Copyright

    Publication Year: 2005 , Page(s): iv
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  • 8th Euromicro Conference on Digital System Design - Table of contents

    Publication Year: 2005 , Page(s): v - x
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  • Message from the Program Chair

    Publication Year: 2005 , Page(s): xi - xii
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  • Conference Committees

    Publication Year: 2005 , Page(s): xiii
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  • Multi-media applications and imprecise computation

    Publication Year: 2005 , Page(s): 2 - 7
    Cited by:  Papers (22)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (216 KB) |  | HTML iconHTML  

    As feature sizes continue to decrease and clock rates and device count on a VLSI chip increase, it becomes increasingly more difficult to maintain yields at their present levels. Process variation, noise and spot defects create very costly problems for our industry. Luckily, in the domain of multi-media, there exists a large body of functions where computational results need not always be correct. We show that for many VLSI implementations of signal processing algorithms, such as MPEG and JPEG encoders, a significant proportion of chips having low levels of defects provide erroneous but acceptable results. We introduce the concept of error-tolerance, and mention related issues needed to support this concept, including ways for specifying performance, design techniques that consider yield, test techniques for quantifying erroneous behavior, and finally the issue of marketing. The motivation for this work is to significantly increase the effective yield of a process, encourage the implementation of complex data processing chips, and drastically reduce chip costs. View full abstract»

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  • Wireless sensor systems - constraints and opportunities

    Publication Year: 2005
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (58 KB) |  | HTML iconHTML  

    Summary form only given. The collaboration of countless tiny sensor nodes in a network promises an enormous potential of novel applications. Advances in miniaturization and integration of electronic and mechanical components will enable sensor nodes with a size of a few cubic millimeters in the near future. At the same time, an ongoing price decline will allow the deployment of sensor networks covering thousands of nodes and, as a consequence, replace conventional wired sensors in many areas. Besides application-specific tasks of a node, the entire network requires a conformance to dynamical system requirements. The development focus changes from the single result of a sensor node to the cumulative result of the network. Consequentially, the following requirements for the design and implementation process of sensor networks arise: (i) sensor networks have to be self-organizing, (ii) sensor nodes must perform tasks of network maintenance, (iii) cooperative processing of tasks should lead to more precise results and new application fields, (iv) sensor networks require security mechanisms that are adaptive to environmental conditions, (v) all algorithms and protocols must be optimized with respect to resources, i.e. energy. The key constraint is energy. While many research teams are investigating better means to store, save, or generate electrical energy, progress is still slow. The paper addresses the inherent limitations and arising research opportunities of wireless sensor networks, both in terms of hardware and software issues. View full abstract»

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  • BIST technique for GALS systems

    Publication Year: 2005 , Page(s): 10 - 16
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (320 KB) |  | HTML iconHTML  

    In this paper a test technique based on the built-in self-test (BIST) is proposed. Our BIST concept is based on hierarchical testing of the digital systems. The presented test scheme is optimized for globally asynchronous locally synchronous (GALS) systems. The BIST technique, described here, is implemented on a GALS baseband processor compliant to the IEEE 802.11a standard. Some results on the performance of our test solution are given. The GALS processor with embedded BIST was fabricated in IHP's 0.25 μm CMOS technology and test results are presented. View full abstract»

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  • Functional vectors generation for RT-level Verilog descriptions based on path enumeration and constraint logic programming

    Publication Year: 2005 , Page(s): 17 - 23
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (264 KB) |  | HTML iconHTML  

    This paper presents a novel method for automatic functional vectors generation from RT-level HDL descriptions based on path coverage and constraint solving. Compared with existing method, the advantage of this method includes: 1) it avoids generating redundant constraints, which will accelerate the test generation process, 2) it solves the problem of how to propagate the internal values to the primary inputs with decision models, 3) it can handle various HDL description styles, and various styles of designs. Experimental results conduct on several practical designs show that our method can efficiently improve the functional vectors generation process. The prototype system has been applied to verify RTL description of a real 32-bits microprocessor core and complex bugs remained hidden in the RTL descriptions are detected. View full abstract»

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  • P2I: an innovative MDA methodology for embedded real-time system

    Publication Year: 2005 , Page(s): 26 - 33
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (408 KB) |  | HTML iconHTML  

    This paper presents a new global MDA design methodology capable to bridge the gap between an abstract specification level and a heterogeneous architecture level while assisting real-time implementation. The P2I contribution is the result of a joint study on abstraction refinement methods and optimized mapping on architecture within a UML based design tools suite including SCADE™ Suite for formal verifications and SynDEx for optimized distributed realtime implementation. The original points of this work are: i) a specification methodology that handles the control flow and the data flow representation, including efficient verifications, ii) a method for parallelism exploration based on abstract resources/performance estimation, iii) a HW/SW mapping approach that refines the specification into explicit HW configurations and the associated SW until executable distributed real-time code. The P2I framework shows how a cooperation of complementary methodologies and CAD tools associated with a relevant architecture can significantly improve the designer productivity, especially in the context of co-modelling for embedded design. View full abstract»

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  • Power-composition profile driven co-synthesis with power management selection for dynamic and leakage energy reduction

    Publication Year: 2005 , Page(s): 34 - 40
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (216 KB) |  | HTML iconHTML  

    Recent research has shown that the combination of dynamic voltage scaling (DVS) and adaptive body biasing (ABB) yields high energy reductions in embedded systems. Nevertheless, the implementation of DVS and ABB requires a significant system cost, making it less attractive for many small systems. In this paper we demonstrate that it is possible to reduce this system cost and to achieve comparable energy saving to that obtained using combined DVS and ABB scheme through a co-synthesis methodology which is aware of the tasks' power-composition profile (the ratio of the dynamic power to the leakage power). In particular, the presented methodology performs a power management selection at the architectural level, i. e., it decides upon which processing elements to be equipped with which power management scheme (DVS, ABB, or combined DVS and ABB) - with the aim to achieve high energy savings at a reduced implementation cost. The proposed technique maps, schedules, and voltage scales applications specified as task graphs with timing constraints. Detailed experiments including a real-life benchmark are conducted to demonstrate the effectiveness of the proposed methodology. View full abstract»

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  • A low-power FIR filter using combined residue and radix-2 signed-digit representation

    Publication Year: 2005 , Page(s): 42 - 47
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (256 KB)  

    This paper presents a FIR filter combining residue (RNS) and radix-2 signed digit (SD) representation. RNS offers parallelization of the computations and SD carry-free additions. The moduli set {2n-1, 2n, 2n+1} is used reducing the complexity of the RNS arithmetic units. The evaluated filters have 8, 12 and 16 taps, binary word lengths between 16 and 64 bits, and have been synthesized using a UMC 0.13 μm CMOS cell library with 8 metal layers. Power, delay, and area comparisons are made with equivalent 2's complement designs. The area-delay and area-delay-power products shows that reduction in both power and area at the same filter throughput can be expected. View full abstract»

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  • Approximating trigonometric functions with the laws of sines and cosines using the logarithmic number system

    Publication Year: 2005 , Page(s): 48 - 53
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (232 KB) |  | HTML iconHTML  

    A new algorithm is given for computing trigonometric functions using the logarithmic number system (LNS). Based on the laws of sines and cosines, the algorithm uses novel addressing of ROMs with the middle-order bits of the LNS representation. Error analysis and simulation show the algorithm is accurate to 22 bits when intermediate steps are performed with 23-bit precision LNS. A VLIW software implementation having throughput of one trigonometric result every 17 cycles is suggested that uses special instructions to access small ROMs containing logarithmic sines and cosines. Also, the proposed algorithm can be implemented fully in hardware having throughput of one trigonometric result every one or two cycles using minor low-cost modifications to an existing LNS ALU design. View full abstract»

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  • Improvement of the fault coverage of the pseudo-random phase in column-matching BIST

    Publication Year: 2005 , Page(s): 56 - 63
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (328 KB) |  | HTML iconHTML  

    Several methods improving the fault coverage in mixed-mode BIST are presented in this paper. The test is divided into two phases: the pseudo-random and deterministic. Maximum of faults should be detected by the pseudo-random phase, to reduce the number of faults to be covered in the deterministic one. We study the properties of different pseudo-random pattern generators. Their successful ness in fault covering strictly depends on the tested circuit. We examine properties of LFSRs and cellular automata. Four methods enhancing the pseudo-random fault coverage have been proposed. Then we propose a universal method to efficiently compute test weights. The observations are documented on some of the standard ISCAS benchmarks and the final BIST circuitry is synthesized using the column-matching method. View full abstract»

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  • Characterization of wavelet-based image coding systems for algorithmic fault detection

    Publication Year: 2005 , Page(s): 64 - 71
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (256 KB) |  | HTML iconHTML  

    This paper presents a methodology for characterizing the behaviour of wavelet-based image coding systems in the presence of faults. This is a previous step in the development of efficient concurrent error detection techniques for such systems. The faulty behaviour of complex signal processing systems is better described at the algorithmic level (i.e., checking the accomplishment of a given functional property by large blocks of data) rather than using the ''classical'' approach at the structural (i.e., building block) level. Therefore, the issues related to algorithmic fault detection are addressed. Two different platforms for error characterization are presented and their main characteristics are discussed. Experimental results are presented that prove the suitability of the proposed methodology for the target application. View full abstract»

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  • Improved fault emulation for synchronous sequential circuits

    Publication Year: 2005 , Page(s): 72 - 78
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (224 KB) |  | HTML iconHTML  

    Current paper presents new alternatives for accelerating the task of fault simulation for sequential circuits by hardware emulation on FPGA. Fault simulation is an important subtask in test pattern generation and it is frequently used throughout the test generation process. The problems associated to fault emulation for sequential circuits are explained and alternative implementations are discussed. An environment for hardware emulation of fault simulation is presented. It incorporates hardware support for fault dropping. The proposed approach allows simulation speed-up of 40 to 500 times as compared to the state-of-the-art in fault simulation. Average speedup provided by the method is 250 that is about an order of magnitude higher than previously cited in the literature. Based on the experiments, we can conclude that it is beneficial to use emulation when large numbers of test vectors is required. View full abstract»

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  • Defect-oriented test- and layout-generation for standard-cell ASIC designs

    Publication Year: 2005 , Page(s): 79 - 82
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (264 KB) |  | HTML iconHTML  

    This work shows a new concept to extend the hierarchical approach of standard-cell circuit design into the area of defect-oriented test pattern generation. For this purpose test patterns to detect shorts for each standard-cell are created separately. A new defect-oriented test generator (DOT) is using these single cell test pattern lists to create test patterns for the complete circuit. Additionally, test patterns for the routing network will be created. This work targets mainly shorts, but also other defects can be treated in a similar way. In order to generate tests only for relevant combinations of shorted nodes, the critical area for both the cells and the routing network is determined separately and the probability for each short is computed. Shorts inside the routing network can show sequential behaviour. The proposed test pattern generator is also able to find tests for such kind of defects. As the effort to test sequential defects can vary from short to short, a new testability analysis is presented. Based on this analysis a redesign of the circuit layout is proposed. This "layout for testability" approach is therefore a defect oriented equivalent for "design for testability" methods. View full abstract»

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  • Power-constrained hybrid BIST test scheduling in an abort-on-first-fail test environment

    Publication Year: 2005 , Page(s): 83 - 86
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (176 KB) |  | HTML iconHTML  

    This paper presents a method for power-constrained system-on-chip test scheduling in an abort-on-first-fail environment where the test is terminated as soon as a fault is detected. We employ the defect probabilities of individual cores to guide the scheduling, such that the expected total test time is minimized and the peak power constraint is satisfied. Based on a hybrid BIST architecture where a combination of deterministic and pseudorandom test sequences is used, the power-constrained test scheduling problem can be formulated as an extension of the two-dimensional rectangular packing problem and a heuristic has been proposed to calculate the near optimal order of different test sequences. The method is also generalized for both test-per-clock and test-per-scan approaches. Experimental results have shown that the proposed heuristic is efficient to find a near optimal test schedule with a low computation overhead. View full abstract»

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  • Hardware virtual components compliant with communication system standards

    Publication Year: 2005 , Page(s): 88 - 95
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (320 KB) |  | HTML iconHTML  

    In this paper, we focus on the design of a communication system based on reusing IP cores. Traditional methods for designing hardware cores for this kind of applications use a RTL specification. However, they suffer from heavy limitations that prevent them from efficiently addressing the algorithmic complexity and the high flexibility required by the various application profiles. For this reason, we propose to raise the abstraction level of the specification and introduce the notion of architectural flexibility by benefiting from the emerging high-level synthesis tools. From a single behavioral-level VHDL specification, we are able to generate a variety of architectures, compliant with the most important communication standards. This technique has been successfully applied to the most important IP cores (synchronization IP, Viterbi IP and Reed-Solomon decoder IP cores) of the DVB-DSNG digital video-broadcasting standard. View full abstract»

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  • High-level synthesis in latency insensitive system methodology

    Publication Year: 2005 , Page(s): 96 - 101
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (248 KB) |  | HTML iconHTML  

    This paper presents our contribution in terms of synchronization processor to a SoC design methodology based on the theory of the latency insensitive systems (US). This methodology 1) promotes pre-developed IPs intensive reuse, 2) segments inter-IPs interconnects with relay stations to break critical paths and 3) brings robustness to data stream irregularities to IPs by encapsulation into a synchronization wrapper. Our contribution consists of IP encapsulation into a new wrapper model containing a synchronization processor, which speed and area are optimized and synthesizability guaranteed. The main benefit of our approach is to preserve the local IP performances when encapsulating them. This approach is part of the RNRT ALIPTA project which targets design automation of intensive digital signal processing systems with GAUT, a high-level synthesis tool. View full abstract»

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  • Embedded object architecture

    Publication Year: 2005 , Page(s): 102 - 107
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (312 KB) |  | HTML iconHTML  

    Traditionally, the embedded system design process demands a considerable amount of expertise, time and money. This makes developing embedded systems impossible for many companies, and in research facilities it hinders the testing of new research results with real embedded systems. We previously presented an easy and fast embedded system development concept based on embedded objects. The embedded object concept (EOC) utilizes common object oriented methods used in software by applying them to combined Lego-like software-hardware entities. This concept enables people without comprehensive knowledge in electronics design to create new embedded systems. In this paper we present a physical and logical architecture for this concept. View full abstract»

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  • An effective framework for enabling the reuse of external soft IP

    Publication Year: 2005 , Page(s): 108 - 111
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (152 KB) |  | HTML iconHTML  

    Intellectual property (IP) reuse is essential for meeting the challenges of system-on-a-chip (SoC) design productivity improvement, design quality and meeting time-to-market goals. Recent trend in the design of complex SoC is doing a joint development with the customer, where it is required to integrate some of their IPs. In such a scenario, the usual paradigm followed for reuse has to be enhanced beyond the state of the art to meet the design goals. This paper describes the reuse framework that has been successfully applied during such a joint development program. The methodology consists of imposing a specified degree of compliance for internal checklists comprising of code quality, design quality, verification quality, and testability checks, and aligning on the goals for design verification and test coverage. Customized enhancements to the IPs to meet the SoC design goals are presented. View full abstract»

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  • A novel method of two-stage decomposition dedicated for PAL-based CPLDs

    Publication Year: 2005 , Page(s): 114 - 121
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (368 KB) |  | HTML iconHTML  

    A PAL-based logic block is the core of great majority of contemporary CPLD devices. The purpose of the paper is to present a novel method of two-stage PAL decomposition. The idea of the method consist in sequential search for a decomposition providing feasibility of implementation of the free block in a PAL-based logic block containing a limited number of product terms. The proposed approach is an alternative to the classical method based on two-level minimization of separate single-output functions. Results of experiments, which are also presented, prove that the proposed algorithm leads to significant reduction of chip area in relation to the classical method, especially for CPLD structures consisting of PAL-based logic blocks containing 2i (a power of 2) product terms. View full abstract»

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  • An advanced minimization technique for multiple valued multiple output logic expressions using LUT and realization using current mode CMOS

    Publication Year: 2005 , Page(s): 122 - 126
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (184 KB) |  | HTML iconHTML  

    We proposed an advanced minimization method for multiple valued multiple output functions in this paper. We extracted the shared sub functions with a proposed heuristic method to pair the functions. New minimization approach for multiple valued functions has also been proposed where we used Kleenean coefficients and we used LUT to reduce the complexity as well. Our minimization method reduces the number of implicants significantly. The realization of the minimized circuits has also been shown using current mode CMOS. View full abstract»

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