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8th Euromicro Conference on Digital System Design (DSD'05)

Aug. 30 2005-Sept. 3 2005

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  • Proceedings. 8th Euromicro Conference on Digital System Design

    Publication Year: 2005
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  • 8th Euromicro Conference on Digital System Design - Title Page

    Publication Year: 2005, Page(s):i - iii
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  • 8th Euromicro Conference on Digital System Design - Copyright

    Publication Year: 2005, Page(s): iv
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  • 8th Euromicro Conference on Digital System Design - Table of contents

    Publication Year: 2005, Page(s):v - x
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  • Message from the Program Chair

    Publication Year: 2005, Page(s):xi - xii
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  • Conference Committees

    Publication Year: 2005, Page(s): xiii
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  • Multi-media applications and imprecise computation

    Publication Year: 2005, Page(s):2 - 7
    Cited by:  Papers (32)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (216 KB) | HTML iconHTML

    As feature sizes continue to decrease and clock rates and device count on a VLSI chip increase, it becomes increasingly more difficult to maintain yields at their present levels. Process variation, noise and spot defects create very costly problems for our industry. Luckily, in the domain of multi-media, there exists a large body of functions where computational results need not always be correct.... View full abstract»

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  • Wireless sensor systems - constraints and opportunities

    Publication Year: 2005
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (58 KB) | HTML iconHTML

    Summary form only given. The collaboration of countless tiny sensor nodes in a network promises an enormous potential of novel applications. Advances in miniaturization and integration of electronic and mechanical components will enable sensor nodes with a size of a few cubic millimeters in the near future. At the same time, an ongoing price decline will allow the deployment of sensor networks cov... View full abstract»

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  • BIST technique for GALS systems

    Publication Year: 2005, Page(s):10 - 16
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB) | HTML iconHTML

    In this paper a test technique based on the built-in self-test (BIST) is proposed. Our BIST concept is based on hierarchical testing of the digital systems. The presented test scheme is optimized for globally asynchronous locally synchronous (GALS) systems. The BIST technique, described here, is implemented on a GALS baseband processor compliant to the IEEE 802.11a standard. Some results on the pe... View full abstract»

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  • Functional vectors generation for RT-level Verilog descriptions based on path enumeration and constraint logic programming

    Publication Year: 2005, Page(s):17 - 23
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (264 KB) | HTML iconHTML

    This paper presents a novel method for automatic functional vectors generation from RT-level HDL descriptions based on path coverage and constraint solving. Compared with existing method, the advantage of this method includes: 1) it avoids generating redundant constraints, which will accelerate the test generation process, 2) it solves the problem of how to propagate the internal values to the pri... View full abstract»

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  • P2I: an innovative MDA methodology for embedded real-time system

    Publication Year: 2005, Page(s):26 - 33
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB) | HTML iconHTML

    This paper presents a new global MDA design methodology capable to bridge the gap between an abstract specification level and a heterogeneous architecture level while assisting real-time implementation. The P2I contribution is the result of a joint study on abstraction refinement methods and optimized mapping on architecture within a UML based design tools suite including SCADE™ Suite for fo... View full abstract»

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  • Power-composition profile driven co-synthesis with power management selection for dynamic and leakage energy reduction

    Publication Year: 2005, Page(s):34 - 40
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (216 KB) | HTML iconHTML

    Recent research has shown that the combination of dynamic voltage scaling (DVS) and adaptive body biasing (ABB) yields high energy reductions in embedded systems. Nevertheless, the implementation of DVS and ABB requires a significant system cost, making it less attractive for many small systems. In this paper we demonstrate that it is possible to reduce this system cost and to achieve comparable e... View full abstract»

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  • A low-power FIR filter using combined residue and radix-2 signed-digit representation

    Publication Year: 2005, Page(s):42 - 47
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (256 KB)

    This paper presents a FIR filter combining residue (RNS) and radix-2 signed digit (SD) representation. RNS offers parallelization of the computations and SD carry-free additions. The moduli set {2n-1, 2n, 2n+1} is used reducing the complexity of the RNS arithmetic units. The evaluated filters have 8, 12 and 16 taps, binary word lengths between 16 and 64 bits, and h... View full abstract»

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  • Approximating trigonometric functions with the laws of sines and cosines using the logarithmic number system

    Publication Year: 2005, Page(s):48 - 53
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (232 KB) | HTML iconHTML

    A new algorithm is given for computing trigonometric functions using the logarithmic number system (LNS). Based on the laws of sines and cosines, the algorithm uses novel addressing of ROMs with the middle-order bits of the LNS representation. Error analysis and simulation show the algorithm is accurate to 22 bits when intermediate steps are performed with 23-bit precision LNS. A VLIW software imp... View full abstract»

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  • Improvement of the fault coverage of the pseudo-random phase in column-matching BIST

    Publication Year: 2005, Page(s):56 - 63
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB) | HTML iconHTML

    Several methods improving the fault coverage in mixed-mode BIST are presented in this paper. The test is divided into two phases: the pseudo-random and deterministic. Maximum of faults should be detected by the pseudo-random phase, to reduce the number of faults to be covered in the deterministic one. We study the properties of different pseudo-random pattern generators. Their successful ness in f... View full abstract»

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  • Characterization of wavelet-based image coding systems for algorithmic fault detection

    Publication Year: 2005, Page(s):64 - 71
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (256 KB) | HTML iconHTML

    This paper presents a methodology for characterizing the behaviour of wavelet-based image coding systems in the presence of faults. This is a previous step in the development of efficient concurrent error detection techniques for such systems. The faulty behaviour of complex signal processing systems is better described at the algorithmic level (i.e., checking the accomplishment of a given functio... View full abstract»

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  • Improved fault emulation for synchronous sequential circuits

    Publication Year: 2005, Page(s):72 - 78
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (224 KB) | HTML iconHTML

    Current paper presents new alternatives for accelerating the task of fault simulation for sequential circuits by hardware emulation on FPGA. Fault simulation is an important subtask in test pattern generation and it is frequently used throughout the test generation process. The problems associated to fault emulation for sequential circuits are explained and alternative implementations are discusse... View full abstract»

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  • Defect-oriented test- and layout-generation for standard-cell ASIC designs

    Publication Year: 2005, Page(s):79 - 82
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (264 KB) | HTML iconHTML

    This work shows a new concept to extend the hierarchical approach of standard-cell circuit design into the area of defect-oriented test pattern generation. For this purpose test patterns to detect shorts for each standard-cell are created separately. A new defect-oriented test generator (DOT) is using these single cell test pattern lists to create test patterns for the complete circuit. Additional... View full abstract»

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  • Power-constrained hybrid BIST test scheduling in an abort-on-first-fail test environment

    Publication Year: 2005, Page(s):83 - 86
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (176 KB) | HTML iconHTML

    This paper presents a method for power-constrained system-on-chip test scheduling in an abort-on-first-fail environment where the test is terminated as soon as a fault is detected. We employ the defect probabilities of individual cores to guide the scheduling, such that the expected total test time is minimized and the peak power constraint is satisfied. Based on a hybrid BIST architecture where a... View full abstract»

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  • Hardware virtual components compliant with communication system standards

    Publication Year: 2005, Page(s):88 - 95
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB) | HTML iconHTML

    In this paper, we focus on the design of a communication system based on reusing IP cores. Traditional methods for designing hardware cores for this kind of applications use a RTL specification. However, they suffer from heavy limitations that prevent them from efficiently addressing the algorithmic complexity and the high flexibility required by the various application profiles. For this reason, ... View full abstract»

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  • High-level synthesis in latency insensitive system methodology

    Publication Year: 2005, Page(s):96 - 101
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (248 KB) | HTML iconHTML

    This paper presents our contribution in terms of synchronization processor to a SoC design methodology based on the theory of the latency insensitive systems (US). This methodology 1) promotes pre-developed IPs intensive reuse, 2) segments inter-IPs interconnects with relay stations to break critical paths and 3) brings robustness to data stream irregularities to IPs by encapsulation into a synchr... View full abstract»

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  • Embedded object architecture

    Publication Year: 2005, Page(s):102 - 107
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB) | HTML iconHTML

    Traditionally, the embedded system design process demands a considerable amount of expertise, time and money. This makes developing embedded systems impossible for many companies, and in research facilities it hinders the testing of new research results with real embedded systems. We previously presented an easy and fast embedded system development concept based on embedded objects. The embedded o... View full abstract»

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  • An effective framework for enabling the reuse of external soft IP

    Publication Year: 2005, Page(s):108 - 111
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (152 KB) | HTML iconHTML

    Intellectual property (IP) reuse is essential for meeting the challenges of system-on-a-chip (SoC) design productivity improvement, design quality and meeting time-to-market goals. Recent trend in the design of complex SoC is doing a joint development with the customer, where it is required to integrate some of their IPs. In such a scenario, the usual paradigm followed for reuse has to be enhanced... View full abstract»

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  • A novel method of two-stage decomposition dedicated for PAL-based CPLDs

    Publication Year: 2005, Page(s):114 - 121
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB) | HTML iconHTML

    A PAL-based logic block is the core of great majority of contemporary CPLD devices. The purpose of the paper is to present a novel method of two-stage PAL decomposition. The idea of the method consist in sequential search for a decomposition providing feasibility of implementation of the free block in a PAL-based logic block containing a limited number of product terms. The proposed approach is an... View full abstract»

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  • An advanced minimization technique for multiple valued multiple output logic expressions using LUT and realization using current mode CMOS

    Publication Year: 2005, Page(s):122 - 126
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (184 KB) | HTML iconHTML

    We proposed an advanced minimization method for multiple valued multiple output functions in this paper. We extracted the shared sub functions with a proposed heuristic method to pair the functions. New minimization approach for multiple valued functions has also been proposed where we used Kleenean coefficients and we used LUT to reduce the complexity as well. Our minimization method reduces the ... View full abstract»

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