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SOC Conference, 2005. Proceedings. IEEE International

Date 25-28 Sept. 2005

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Displaying Results 1 - 25 of 92
  • [Cover]

    Page(s): C1
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  • Proceedings. IEEE International SOC Conference (IEEE Cat. No. 05TH8822)

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  • Copyright page

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  • Message from the General Chair

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  • Message From the Technical Program Chair

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  • Program-at-a Glance

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  • 2005 SOCC Organizing Committee

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  • List of reviewers

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  • Table of contents

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  • Author index

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  • Session quick index

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  • 3.48mW 2.4GHz range Frequency Synthesizer Architecture with Two-Point Channel Control for Fast Settling Performance

    Page(s): 1 - 6
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2046 KB) |  | HTML iconHTML  

    A new frequency synthesizer architecture with low-power and very short settling time is introduced for 2.4GHz ZigBee applications. It uses two-point channel control with divider control and direct VCO control. A DAC with tunable gain is used along with a linearized varactor for the direct VCO control path. Despite the use of an integer-N architecture with 50kHz loop bandwidth, we have achieved a frequency settling time of less than 10musec for 80MHz frequency jumping from 2400MHz. The proposed modified-TSPC circuit topology with 2-transistor stacks operational with lower supply voltage is used for the high frequency divider circuits. With a lowered supply voltage of 1.0V, the power consumption is significantly reduced and so is the switching noise induced by TSPC and digital circuits. With the -112 dBc/Hz phase noise at 1MHz offset from 2.44GHz, total power consumption using 0.18mum CMOS technology is only 3.48mW View full abstract»

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  • A Low Jitter Programmable Frequency Synthesizer for 4.25Gbps Serial Link Applications

    Page(s): 7 - 10
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2142 KB) |  | HTML iconHTML  

    This paper describes a wide-range programmable frequency synthesizer building block for 4.25Gbps serial link applications. A unique feature of the design is the use of variable gain charge pumps to adjust loop gain as well as damping in order to minimize output jitter. The synthesizer architecture includes pre and post dividers to maximize programmability. A novel implementation of the high speed divide circuit is also described View full abstract»

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  • 3.125Gbps Reference-less Clock and Data Recovery using 4X Oversampling

    Page(s): 11 - 14
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1900 KB) |  | HTML iconHTML  

    In this paper, a clock and data recovery (CDR) circuit for a serial link with a half rate 4times oversampling phase and frequency detector structure without a reference clock is described. The PD and FD are designed by 4times oversampling method. The PD, which uses bang-bang method, finds the phase error by generating four up/down signal and the FD, which uses the rotational method, finds the frequency error by generating up/down signal made by the PD output. And the six signals of the PD and the FD control an amount of current that flows through the charge pump. The VCO composed of four differential buffer stages generates eight differential clocks. Proposed circuit is designed using the TSMC 0.18mum CMOS technology and operating voltage is 1.8V View full abstract»

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  • Digital clock frequency doubler

    Page(s): 15 - 18
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1798 KB) |  | HTML iconHTML  

    A digital clock frequency doubler capable of handling large variation in input duty cycle and PVT (process, voltage and temperature) is presented. Unlike the conventional clock frequency doublers, the proposed circuit doesn't require 50% duty cycle for doubling the input clock frequency and consumes lower silicon area. A digital algorithm is used to generate output frequency and an inbuilt PVT compensation mechanism ensures good frequency stability if there is any change in PVT. The circuit has been designed in 90nm CMOS process with input frequency range of 10MHz to 30MHz and silicon results show less than 0.2% of average frequency error View full abstract»

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  • Power minimization of rotary clock design

    Page(s): 19 - 24
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (820 KB) |  | HTML iconHTML  

    Rotary clock is a recently proposed clock distribution technique based on wave propagation in transmission lines. In this paper, we present the first design methodology to minimize the power dissipation of rotary clock structures. Specifically, our scheme derives a rotary clock array that dissipates minimal power while satisfying the clock dimension requirement and oscillating at the target frequency with the given clock load. Experimental results have demonstrated that, for designs with operating frequencies ranging from 0.5 to 5 Gigahertz, our approach achieves a 24.3% power reduction on the average compared with power-unaware design methods. Furthermore, rotary clock designs implemented using our scheme consume as low as 31% power of the optimal conventional clock tree designs View full abstract»

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  • Thermal-aware mapping and placement for 3-D NoC designs

    Page(s): 25 - 28
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3119 KB) |  | HTML iconHTML  

    Networks on chip (NoC) and 3D integrated circuits have been proposed as solutions to the ever-growing interconnect woes surrounding systems-on-chip. 3D designs however suffer from hotspot creation, due to the increase in the power density of parts of the chip. In this paper, we propose the use of a genetic algorithm for a thermal and communication aware mapping and placement of application tasks on 3D NoC environment. Our results show a significant reduction in system temperature when compared to a random mapping and placement, and provide an encouraging situation for migration to the 3D design space View full abstract»

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  • An IR drop-driven placer for standard cells in a SOC design

    Page(s): 29 - 32
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2383 KB) |  | HTML iconHTML  

    A partition-based IR drop-driven algorithm is proposed for standard cell placement. Different cost functions for reducing IR drop are used in the horizontal cut and vertical cut partitioning processes. In addition to minimizing the total wire length, we balance the power consumption of the two partitions during the horizontal cut partitioning process. During the vertical cut partitioning process, we move the cells with higher power consumption closer to the power sources to reduce the maximum IR drop of the row. After placement is finished, we apply a greedy placement refinement process to further reduce the value of the maximum IR drop. Each standard cell row is modeled with an equivalent conductance model. Then the IR drop of each row is calculated and analyzed. We compare the placement generated by the proposed approach with the wire length-driven placement. On average, the proposed approach improves the value of maximum IR drop by 51%. Therefore, it reduces the need to add power straps on the chip and more routing resources are saved View full abstract»

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  • Combined simulator statistics and block code sampling to study performance enhancement of microarchitecture

    Page(s): 33 - 36
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1528 KB) |  | HTML iconHTML  

    This paper presents a simple approach combining the statistics of simulation and block code sampling to study the performance enhancement of the microarchitecture with duplicated pipelines (enhanced microarchitectures). We collect the statistics from the simulation of EEMBC benchmark code on a TriCore™ 2.0 implementation and use them to sample blocks of code and simulate different enhanced microarchitectures. The new simulation results are used to analyse the performance benefits of each microarchitecture enhancement, which can narrow down the design space exploration. View full abstract»

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  • A CMOS Voltage Reference with Temperature Sensor using Self-PTAT Current Compensation

    Page(s): 37 - 42
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (568 KB) |  | HTML iconHTML  

    An all-CMOS circuit for combined voltage reference and temperature sensor is proposed. For voltage reference design, a self-PTAT current is generated for compensating a diode-connected NMOS transistor for achieving temperature-independent purpose. In addition, an ultra linear temperature sensor can be realized and achieved simultaneously. The circuit topology is very suitable for SoC integration. The voltage reference provides a stable voltage for analog circuit. Moreover, the temperature sensor increases the system reliability by predicting eventual faults caused by excessive chip temperatures View full abstract»

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  • Hybrid Voltage and Current References Based on Double ZTC Points

    Page(s): 43 - 46
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1265 KB) |  | HTML iconHTML  

    A novel design idea, based on the double zero temperature coefficient (DZTC) points, for voltage and current references with temperature and power-supply independency is proposed. A circuit topology is developed for realization of this idea. It does not only provide two voltage references, but also give one current reference, simultaneously. Furthermore, the circuit is very suitable for mixed-signal, VLSI, and SOC design, because only pure MOSFET transistors are used. The simulation results by using 0.35mum CMOS technology show the DZTC voltage and current references with very good temperature performance, comparing with previous works View full abstract»

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  • Automatic gain control circuit for power line communication application

    Page(s): 47 - 50
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1569 KB) |  | HTML iconHTML  

    A CMOS automatic gain control (AGC) circuit for power line networking application is presented. In this work, the AGC can effectively lock the amplitude of the input signal within 0.2mus. Implemented in 0.35mum CMOS process, the dynamic range of the variable gain amplifier is more than 36dB and the bandwidth of its forward path is 85MHz. It is designed for power line communication application and is fed from a single 3.3-V power supply. Its power consumption is 4.2mW and area of the AGC is 630 times 700 mum2 View full abstract»

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  • CMOS SoC for irrigation control

    Page(s): 51 - 54
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2032 KB) |  | HTML iconHTML  

    A CMOS VLSI system on chip, designed for irrigation control applications was developed. The SoC features include wireless communication capability, data processing, sensor signal acquisition and actuator control. A power saving strategy provides long-term autonomy with standard energy sources. Application software and dedicated software development CAD tools were also implemented in this design effort. View full abstract»

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  • A Flow Graph Technique for DFT Controller Modification

    Page(s): 55 - 60
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3224 KB) |  | HTML iconHTML  

    This paper presents a novel DFT method which requires very small modification to a controller in RT-level description of a circuit. The control/data flow graph (CDFG) representation of an RTL circuit is used for analyzing the testability of individual RT-level operations within a hierarchical test technique. Using a non-scan arrangement, existing data paths are utilized to provide controllability and observability to RT-level operations. Furthermore, additional data paths are introduced by altering the controller states or signals. Post behavioral synthesis information and pre-computed test vectors of the individual modules are utilized. This method considerably reduces the test application time by ignoring unnecessary control states in the test process View full abstract»

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  • Testing system-on-a-chip using artificial immune system

    Page(s): 61 - 64
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (616 KB) |  | HTML iconHTML  

    A novel system-on-a-chip (SoC) test scheme taking inspiration from the human immune system is presented. Such a scheme is based on the negative-selection mechanism which provides the human body with the capability to discriminate between the self (body's own cell) and any foreign cell (non-self). Based on this, it is design a test scheme which is emulated and executed by an embedded processor in order to test other cores of the SoC. Experimental results showing the effectivity of the proposed scheme are presented. View full abstract»

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