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13th Symposium on High Performance Interconnects (HOTI'05)

Date 17-19 Aug. 2005

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Displaying Results 1 - 25 of 35
  • Proceedings. 13th Symposium on High Performance Interconnects

    Publication Year: 2005
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  • 13th Symposium on High Performance Interconnects - Title Page

    Publication Year: 2005, Page(s):i - iii
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  • 13th Symposium on High Performance Interconnects - Copyright Page

    Publication Year: 2005, Page(s): iv
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  • 13th Symposium on High Performance Interconnects - Table of contents

    Publication Year: 2005, Page(s):v - vii
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  • General Chairs’ Message

    Publication Year: 2005, Page(s): viii
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  • Message from the Program Co-Chairs

    Publication Year: 2005, Page(s):ix - x
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  • Committees

    Publication Year: 2005, Page(s):xi - xii
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  • Using the open network lab

    Publication Year: 2005, Page(s):2 - 3
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (35 KB) | HTML iconHTML

    The Open Network Laboratory is a resource designed to enable experimental evaluation of advanced networking concepts in a realistic operating environment. The laboratory is built around a set of open-source, extensible, high performance routers, which can be accessed by remote users through a remote laboratory interface (RLI). The RLI allows users to configure the testbed network, run applications... View full abstract»

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  • Quality of service in global grid computing

    Publication Year: 2005, Page(s):4 - 5
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (47 KB) | HTML iconHTML

    This tutorial tries to address some of the issue related to the keywords present in Foster's grid computing definition. Specifically it tackles the problem of providing global grid computing applications with a network infrastructure able to guarantee quality of service. After reviewing the basics of grid computing, this tutorial focuses on specific network infrastructure issues. Quality of servic... View full abstract»

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  • Internet infrastructure security

    Publication Year: 2005, Page(s):6 - 7
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (43 KB) | HTML iconHTML

    The goal of this tutorial is to provide a comprehensive understanding of the state-of-the-art research and practice in Internet infrastructure security, to its audience. In addition to discussions on attacks and counter-measures, issues such as performance, scalability, deployability, and high speed implementations will also be discussed. View full abstract»

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  • High-speed networking: a systematic approach to high-bandwidth low-latency communications

    Publication Year: 2005, Page(s):8 - 9
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (41 KB) | HTML iconHTML

    This tutorial presents a comprehensive introduction to all aspects of high-speed networking, based on the book high-speed networking: a systematic approach to high-bandwidth low-latency communication. The target audience includes computer scientists and engineers who may have expertise in a narrow aspect of high-speed networking but want to gain a broader understanding of all aspects of high-speed... View full abstract»

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  • Challenges in building a flat-bandwidth memory hierarchy for a large-scale computer with proximity communication

    Publication Year: 2005, Page(s):13 - 22
    Cited by:  Papers (17)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (584 KB) | HTML iconHTML

    Memory systems for conventional large-scale computers provide only limited bytes/s of data bandwidth when compared to their flop/s of instruction execution rate. The resulting bottleneck limits the bytes/flop that a processor may access from the full memory footprint of a machine and can hinder overall performance. This paper discusses physical and functional views of memory hierarchies and examin... View full abstract»

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  • Optimised global reduction on QsNetII

    Publication Year: 2005, Page(s):23 - 28
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (296 KB) | HTML iconHTML

    In this paper we describe how QsNetII supports reduction, a key collective for massively parallel applications. Results from jobs run on a 512-node quad CPU cluster show excellent scaling, with the average time to execute a 2048 process global sum being 22 microsecs. View full abstract»

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  • Control path implementation for a low-latency optical HPC switch

    Publication Year: 2005, Page(s):29 - 35
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB) | HTML iconHTML

    A crucial part of any high-performance computing system is its interconnection network. In the OSMOSIS project, Corning and IBM are jointly developing a demonstrator interconnect based on optical cell switching with electronic control. Starting from the core set of requirements, we present the system design rationale and show how it impacts the practical implementation. Our focus is on solving the... View full abstract»

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  • Breaking the connection: RDMA deconstructed

    Publication Year: 2005, Page(s):36 - 42
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (176 KB) | HTML iconHTML

    The architecture, design and performance of RDMA (remote direct memory access) over the IBM HPS (high performance switch and adapter) are described. Unlike conventional implementations such as InfiniBand, our RDMA transport model is layered on top of an unreliable datagram interface, while leaving the task of enforcing reliability to the ULP (upper layer protocol). We demonstrate that our model al... View full abstract»

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  • Can memory-less network adapters benefit next-generation infiniband systems?

    Publication Year: 2005, Page(s):45 - 50
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (200 KB) | HTML iconHTML

    InfiniBand is emerging as a high-performance interconnect. It is gaining popularity because of its high performance and open standard. Recently, PCI-Express, which is the third generation high-performance I/O bus used to interconnect peripheral devices, has been released. The third generation of InfiniBand adapters allow applications to take advantage of PCI-Express. PCI-Express offers very low la... View full abstract»

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  • Initial performance evaluation of the Cray SeaStar interconnect

    Publication Year: 2005, Page(s):51 - 57
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (208 KB) | HTML iconHTML

    The Cray SeaStar is a new network interface and router for the Cray Red Storm and XT3 supercomputer. The SeaStar was designed specifically to meet the performance and reliability needs of a large-scale, distributed-memory scientific computing platform. In this paper, we present an initial performance evaluation of the SeaStar. We first provide a detailed overview of the hardware and software featu... View full abstract»

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  • Performance characterization of a 10-Gigabit Ethernet TOE

    Publication Year: 2005, Page(s):58 - 63
    Cited by:  Papers (26)  |  Patents (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (168 KB) | HTML iconHTML

    Though traditional Ethernet based network architectures such as Gigabit Ethernet have suffered from a huge performance difference as compared to other high performance networks (e.g, InfiniBand, Quadrics, Myrinet), Ethernet has continued to be the most widely used network architecture today. This trend is mainly attributed to the low cost of the network components and their backward compatibility ... View full abstract»

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  • Hybrid cache architecture for high speed packet processing

    Publication Year: 2005, Page(s):67 - 72
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (152 KB) | HTML iconHTML

    The exposed memory hierarchies employed in many network processors (NPs) are expensive and hard to be effectively utilized. On the other hand, conventional cache cannot be directly incorporated into NP either because of its low efficiency in locality exploitation for network applications. In this paper, a novel memory hierarchy component, called split control cache, is presented. The proposed sche... View full abstract»

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  • High-speed and low-power network search engine using adaptive block-selection scheme

    Publication Year: 2005, Page(s):73 - 78
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (176 KB) | HTML iconHTML

    A new approach for using block-selection scheme to increase the search throughput of multi-block TCAM-based network search engines is proposed. While the existing methods try to counter and forcibly balance the inherent bias of the Internet traffic, our method takes advantage of it. Our method improves flexibility of table management and gains scalability towards high rates of change in traffic bi... View full abstract»

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  • Design and implementation of a content-aware switch using a network processor

    Publication Year: 2005, Page(s):79 - 85
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (168 KB) | HTML iconHTML

    Cluster based server architectures have been widely used as a solution to overloading in Web servers because of their cost effectiveness, scalability and reliability. A content aware switch can be used to examine the Web requests and distribute them to the servers based on application level information. In this paper, we present the analysis, design and implementation of such a content aware switc... View full abstract»

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  • Impact of grid computing on network operators and HW vendors

    Publication Year: 2005, Page(s):89 - 90
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (42 KB)

    Grid computing is an attempt to make computing work like the power grid. When you run a job, you shouldn't know or care where it runs, so long as it gets done within your constraints (including security). However, in attempting to accomplish this, Grid researchers are presenting network access patterns and loads different from what has been typical of Internet traffic. MPI applications are looking... View full abstract»

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  • A scalable switch for service guarantees

    Publication Year: 2005, Page(s):93 - 99
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (192 KB) | HTML iconHTML

    Operators need routers to provide service guarantees such as guaranteed flow rates and fairness among flows, so as to support real-time traffic and traffic engineering. However, current centralized input-queued router architectures cannot scale to fast line rates while providing these service guarantees. On the other hand, while load-balanced switch architectures that rely on two identical stages ... View full abstract»

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  • Design of randomized multichannel packet storage for high performance routers

    Publication Year: 2005, Page(s):100 - 106
    Cited by:  Papers (8)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (152 KB) | HTML iconHTML

    High performance routers require substantial amounts of memory to store packets awaiting transmission, requiring the use of dedicated memory devices with the density and capacity to provide the required storage economically. The memory bandwidth required for packet storage subsystems often exceeds the bandwidth of individual memory devices, making it necessary to implement packet storage using mul... View full abstract»

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  • Addressing queuing bottlenecks at high speeds

    Publication Year: 2005, Page(s):209 - 224
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (152 KB) | HTML iconHTML

    Modern routers and switch fabrics can have hundreds of input and output ports running at up to 10 Gb/s; 40 Gb/s systems are starting to appear. At these rates, the performance of the buffering and queuing subsystem becomes a significant bottleneck. In high performance routers with more than a few queues, packet buffering is typically implemented using DRAM for data storage and a combination of off... View full abstract»

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