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2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)

Date 23-25 July 2005

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Displaying Results 1 - 25 of 69
  • 16th International Conference on Application-Specific Systems, Architecture and Processors

    Publication Year: 2005
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  • 16th International Conference on Application-Specific Systems, Architecture and Processors - Title Page

    Publication Year: 2005, Page(s):i - iii
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  • 16th International Conference on Application-Specific Systems, Architecture and Processors - Copyright Page

    Publication Year: 2005, Page(s): iv
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  • 16th International Conference on Application-Specific Systems, Architecture and Processors - Table of contents

    Publication Year: 2005, Page(s):v - viii
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  • Message from the Conference Chairs

    Publication Year: 2005, Page(s): ix
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  • Conference Organizers

    Publication Year: 2005, Page(s): xi
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  • Program Committee

    Publication Year: 2005, Page(s): xii
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  • External referees

    Publication Year: 2005, Page(s): xiii
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  • Area - time - power and design effort: the basic tradeoffs in application specific systems

    Publication Year: 2005, Page(s):3 - 6
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (144 KB) | HTML iconHTML

    Application specific is always a tradeoff among competing design goals (or design parameters). In addition to the well established area (cost) - time (performance) - power metrics specific applications imply a relatively limited market so design cost becomes an especially important consideration. As technology offers increasing transistor density with lower cost power constraints limit frequency a... View full abstract»

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  • Using symbolic feasibility tests during design space exploration of heterogeneous multi-processor systems

    Publication Year: 2005, Page(s):9 - 14
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (248 KB) | HTML iconHTML

    The task of automatic design space exploration of heterogeneous multi-processor systems is often tackled with evolutionary algorithms. In this paper, we propose a novel approach in combining evolutionary algorithms with symbolic techniques in order to improve the convergence speed. The main idea is to guide the search towards the feasible region by utilizing symbolic techniques. We present experim... View full abstract»

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  • Expression synthesis in process networks generated by LAURA

    Publication Year: 2005, Page(s):15 - 21
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (373 KB) | HTML iconHTML

    The COMPAAN/LAURA (Stefanov et al., 2004) tool chain maps nested loop applications written in Matlab onto reconfigurable platforms, such as FPGAs. COMPAAN rewrites the original Matlab application as a process network in which the control is parameterized and distributed. This control is given as parameterized polytopes that are expressed in terms of pseudo-linear expressions. These expressions can... View full abstract»

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  • Artificial deadlock detection in process networks for ECLIPSE

    Publication Year: 2005, Page(s):22 - 27
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB) | HTML iconHTML

    Kahn process network (KPN) is a popular model of computation for describing streaming applications. In a KPN model, processes communicate through unbounded unidirectional FIFOs. When theoretically unbounded FIFOs are implemented using finite memory, artificial deadlocks can occur due to one or more FIFOs having insufficient sizes. Generally, a system designer must be able to make a design time tra... View full abstract»

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  • Hardware/software interface for multi-dimensional processor arrays

    Publication Year: 2005, Page(s):28 - 35
    Cited by:  Papers (2)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB) | HTML iconHTML

    On most recent systems on chip, the performance bottleneck is the on-chip communication medium, bus or network. Multimedia applications require a large communication bandwidth between the processor and graphic hardware accelerators, hence an efficient communication scheme using burst mode is mandatory. In the context of data-flow hardware accelerators, we approach this problem as a classical resou... View full abstract»

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  • Casablanca II: implementation of a real-time RISC core for embedded systems

    Publication Year: 2005, Page(s):36 - 42
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (224 KB) | HTML iconHTML

    We extended general-purpose RISC processor architecture and developed a new RISC core, Casablanca II, for supporting real-time processing in embedded systems. The processor core has multiple register-sets and achieves fast context-switching by automatically changing the active register-set and reducing overheads to save and restore the contents of the registers when exceptions or interruptions occ... View full abstract»

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  • Behavioral specification of control interface for signal processing applications

    Publication Year: 2005, Page(s):43 - 49
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (240 KB) | HTML iconHTML

    Data-driven applications that are mapped onto large-scale systems need to be controlled for (re-)configuration, test and monitoring. Such systems consist of distributed and heterogeneous components. We specify the behavior of a control network independent of the system architecture and independent of the data-driven application. We address particularly the key problem of the interfacing between th... View full abstract»

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  • Speedups from partitioning critical software parts to coarse-grain reconfigurable hardware

    Publication Year: 2005, Page(s):50 - 55
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (216 KB) | HTML iconHTML

    In this paper, we propose a hardware/software partitioning method for improving applications' performance in embedded systems. Critical software parts are accelerated on hardware of a single-chip generic system comprised by an embedded processor and coarse-grain reconfigurable hardware. The reconfigurable hardware is realized by a 2D array of processing elements. The partitioning flow utilizes an ... View full abstract»

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  • A SW/configware codesign methodology for control dominated applications

    Publication Year: 2005, Page(s):56 - 61
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB) | HTML iconHTML

    In this paper, we present a partitioning methodology targeting a dynamically reconfigurable architecture. We first identify this class of architectures and point out the lack of underlying tools and compiler support exploiting, with these architectures, the potential task level parallelism (TLP). The applications in today's and the future embedded systems are more and more control dominated making... View full abstract»

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  • Towards a framework for system-level design of multiprocessor SoC platforms for media processing

    Publication Year: 2005, Page(s):65 - 72
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (256 KB) | HTML iconHTML

    Recently, a number of event-centric models have been proposed for analyzing multimedia applications running on multiprocessor system-on-chip (SoC) platforms. This has given shape to a general framework using which different timing and performance analysis questions can be answered in a single coherent manner. Central to this framework is a model for expressing the timing properties associated with... View full abstract»

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  • Communication-centric SoC design for nanoscale domain

    Publication Year: 2005, Page(s):73 - 78
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (576 KB) | HTML iconHTML

    In the realm of 35nm technology, it becomes possible to have thousands of IP blocks that need to communicate efficiently. Large-scale integration of these blocks onto a single chip makes the use of truly scalable networks-on-chips (NoC) communication architectures inevitable. This paper provides an overview of the outstanding research issues involved in designing application-specific NoC architect... View full abstract»

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  • Using TLM for exploring bus-based SoC communication architectures

    Publication Year: 2005, Page(s):79 - 85
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (280 KB) | HTML iconHTML

    As billion transistor system-on-chips (SoC) become commonplace and design complexity continues to increase, designers are faced with the daunting task of meeting escalating design requirements in shrinking time-to-market windows, and have begun using an IP-based SoC design methodology that permits reuse of key SoC functional components. Since the communication architectures connecting components i... View full abstract»

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  • Exploring design space of VLIW architectures

    Publication Year: 2005, Page(s):86 - 91
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (288 KB) | HTML iconHTML

    Architectures based on very long instruction word (VLIW) have found fertile ground in multimedia electronic appliances thanks to their ability to exploit high degrees of instruction level parallelism (ILP) with a reasonable tradeoff in complexity and silicon costs. Effective compiler support for predicated execution using the hyperblock, drastically increases the ILP even for control-dominated app... View full abstract»

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  • The midlifekicker microarchitecture evaluation metric

    Publication Year: 2005, Page(s):92 - 97
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (632 KB) | HTML iconHTML

    We introduce the midlfekicker metric for evaluating microarchitectures mostly during the design process. We assume a microarchitecture designed at a time T-1 and estimate if a new microarchitecture projected for time T has advantages over the microarchitecture designed at T-1 and remapped on the same technology at time T. We consider that microarchitects minimize the product cycles per instruction... View full abstract»

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  • Design of a hardware accelerator for density based clustering applications

    Publication Year: 2005, Page(s):101 - 106
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (200 KB) | HTML iconHTML

    Data mining is beginning to be widely used in various application fields. Density based clustering algorithms perform data mining by grouping high-density regions of points to form clusters. In recent years, the data sizes and the problem complexity of this algorithm have increased significantly leading to slower execution of the applications. Faster engines that perform the application tasks quic... View full abstract»

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  • Complex fixed-point matrix inversion using transport triggered architecture

    Publication Year: 2005, Page(s):107 - 112
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB) | HTML iconHTML

    Fixed-point simulations for inverting matrices using transport triggered architectures are performed. Several methods are implemented in fixed-point: the Cholesky decomposition as a direct method, Newton iterations as an iterative method, and Strassen Newton algorithm as a combined recursive method. Fixed-point implementations of these matrix inversion algorithms are tested and analyzed. A divisio... View full abstract»

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  • A parallel automaton string matching with pre-hashing and root-indexing techniques for content filtering coprocessor

    Publication Year: 2005, Page(s):113 - 118
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (272 KB) | HTML iconHTML

    We propose a new parallel automaton string matching approach and its hardware architecture for content filtering coprocessor. This new approach can improve the average matching time of the parallel automaton with pre-hashing and root-indexing techniques. The pre-hashing technique uses a hashing function to verify quickly the text against the partial patterns in the automaton, and the root-indexing... View full abstract»

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