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Parallel and Distributed Systems, 2005. Proceedings. 11th International Conference on

Date 20-22 July 2005

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  • 11th International Conference on Parallel and Distributed Systems Workshops - Cover

    Page(s): c1
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  • 11th International Conference on Parallel and Distributed Systems Workshops - Title

    Page(s): i - ii
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  • 11th International Conference on Parallel and Distributed Systems Workshops - Copyright

    Page(s): iv
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  • 11th International Conference on Parallel and Distributed Systems Workshops - Table of contents

    Page(s): v - xxii
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  • Message from the PDES-2005 Chairs

    Page(s): xxiii
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  • PDES-2005 Organizing Committee

    Page(s): xxiv
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  • PDES-2005 Reviewers

    Page(s): xxv
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  • Minimizing Energy via Loop Scheduling and DVS for Multi-Core Embedded Systems

    Page(s): 2 - 6
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (236 KB) |  | HTML iconHTML  

    Low energy consumptions are extremely important in real-time embedded systems, and scheduling is one of the techniques used to obtain lower energy consumptions. In this paper, we propose loop scheduling algorithms for minimizing energy based on rotation scheduling and DVS (dynamic voltage and frequency scaling) for real-time multi-core embedded systems. The experimental results show that our algorithms have better performances than list scheduling and pure ILP (integer linear programming) scheduling with DVS View full abstract»

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  • A Dynamic Node Degree Management Scheme for Energy-efficient Routing Protocols in Wireless Ad Hoc Networks

    Page(s): 7 - 11
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    In mobile devices, the battery-based power is a precious resource. To maximize the network lifetime becomes a challenge issue in MANETs. We found that transmission collision is a problem which affects the energy saving much. If we can reduce the numbers of the transmission collision, we save more power. In this paper, we propose a new mechanism to address this problem and hence prolong network lifetime. Our approach, based on relative neighborhood graph (RNG), adjusts the transmission range according to the degree of the node which is only based on local information. We also suggest appropriate transmission power ranges to some routing protocols such as AODV, DSR and BELLMAN-FORD. Simulation results show that a great improvement of the energy saving for those routing protocols when comparing with the performance of those protocols without applying our mechanism View full abstract»

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  • A Hierarchical Approach for Energy-Aware Distributed Embedded Intelligent Video Surveillance

    Page(s): 12 - 16
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (199 KB) |  | HTML iconHTML  

    Intelligent video surveillance (IVS) offers a large spectrum of different applications that have strict requirements on quality of service (QoS) and energy-efficiency. Recent embedded IVS systems need to deliver compressed video data in high quality while using devices that are partly solar- or battery-powered. In this paper we present PoQoS, a novel hierarchical approach for combined power- and QoS-management in distributed embedded IVS systems. PoQoS allows the implementation of both global and local power- and QoS-adaptation in order to achieve optimal energy/QoS tradeoffs. Furthermore, we present a DSP-based, embedded platform that is used for IVS. It includes QoS-triggered onboard dynamic power management (DPM) that is controlled via Ethernet. We demonstrate the feasibility of PoQoS with a typical IVS-setup and present experimental results View full abstract»

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  • A Code Generation Algorithm for Affine Partitioning Framework

    Page(s): 17 - 21
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    Multiprocessors are about to become prevalent in the PC world. Major CPU vendors such as Intel and Advanced Micro Devices have recently announced their imminent migration to multicore processors. Affine partitioning provides a systematic framework to find asymptotically optimal computation and data decomposition for multiprocessors, including multicore processors. This affine framework uniformly models a large class of high-level optimizations such as loop interchange, reversal, skewing, fusion, fission, re-indexing, scaling, and statement reordering. However, the resulting code after applying affine transformations tends to contain more loop levels and complex conditional expressions. This impacts performance, code readability and debuggability for both programmers and compiler developers. To facilitate the adoption of affine partitioning in industry, we address the above practical issues by proposing a salient two-step algorithm: coalesce and optimize. The coalescing algorithm maintains valid code throughout and improves readability and debuggability. We demonstrate with examples that the optimization algorithm simplifies the resulting loop structures, conditional expressions and array access functions and generates efficient code View full abstract»

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  • Constructing a Memory-Based Distributed Code Storage on Networked Diskless Embedded Systems

    Page(s): 22 - 26
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (181 KB) |  | HTML iconHTML  

    Advances in networking and microprocessor technology have enabled the development of a variety of small, low-cost, and resource-limited embedded systems. Such an embedded system is often diskless due to the weight, size, and cost of a disk. Because of the availability of inexpensive high-speed network cards, most embedded systems are networked, wired or wireless. We propose and implement a memory-based distributed code storage called NFC (networked file cache) for networked diskless embedded systems. NFC utilizes and integrates all available memory resources in a network to form a large-scaled code storage to which all applications in all nodes are allowed to access. To efficiently locate a file in NFC, we present a one-hop file lookup algorithm and a set of cache management algorithms dealing with file migrations and replications. In comparison with a client-server approach, the experimental results show that NFC successfully integrates memory resources in a network to significantly extend code storage and reduce file-access time of a diskless embedded system View full abstract»

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  • Design of a Configurable Embedded Processor Architecture for DSP Functions

    Page(s): 27 - 31
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    Most of the embedded applications are served today by general-purpose processors or special-purpose ASIC processors containing hundreds to thousands of ALUs. While such solutions are efficient, they lack flexibility and are not feasible for certain embedded applications. ASIP(application specific instruction processor) design methodology can not only satisfy the functionality and performance requirements of the embedded systems but also flexible. So it is widely adopted in embedded processor design domain. For the widely adopting of digital signal processing in the embedded applications, this paper studies a configurable VLIW processor architecture based on TTA(transport triggered architecture) for high performance digital signal processing in embedded systems. The methodology of ASIP design is applied and some handle optimizations are taken. It is shown that it has high performance to run the digital signal processing kernel applications, and its simplicity and flexibility encourages for further development with tuned functionality View full abstract»

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  • Cramer-Rao Bound Analysis of Quantized RSSI Based Localization in Wireless Sensor Networks

    Page(s): 32 - 36
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    Localizing sensor nodes in a distributed system of wireless sensors is an essential process for self-organizing wireless sensor networks. Localization is a fundamental problem in wireless sensor networks, and the behavior of localization has not been thoroughly studied. In this paper, we formulate the quantized received signal strength indicator based localization as a parameter estimation problem and derive the Cramer-Rao lower bound for the localization problem. We study the effect of quantization level and network configuration parameters on the lower bound of localization error variance and understand the relationship between network configuration and localization accuracy View full abstract»

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  • Partitioning and Pipelined Scheduling of Embedded System Using Integer Linear Programming

    Page(s): 37 - 41
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (170 KB) |  | HTML iconHTML  

    In this paper, an integer linear programming (ILP) based approach is proposed for integrated hardware/software (HW/SW) partitioning and pipelined scheduling of embedded systems for multimedia applications. The ILP approach not only partitions and maps each computation task of a particular multimedia application onto a component of the heterogeneous multiprocessor architecture, but also schedules and pipelines the execution of these computation tasks while considering communication time. The objective is to minimize the total component cost and the number of pipeline stages subject to the throughput constraint on the pipelined architecture. Experiments on two real multimedia applications are used to demonstrate the effectiveness of the proposed approach View full abstract»

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  • Design and Integration of Parallel Hough-Transform Chips for High-speed Line Detection

    Page(s): 42 - 46
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (197 KB) |  | HTML iconHTML  

    Line detection is often needed in computer vision applications. The Hough transform processing of image data for line detection is robust but time-consuming. With the use of multiple processors, the processing time for Hough transform can be much reduced. In our research, we design an array processor for line-detection based on Hough transform that performs the line-parameter calculation and accumulation for different angles in parallel. Such an array processor together with its parallel peak extraction circuits have been implemented on a single chip. Based on the TSMC 0.35mum CMOS technology, the fabricated chip (with 10 processors) can be run successfully up to the clock rate of 50MHz. This paper presents the SOC design that can be extended to the integration of multiple chips to form a faster system with more parallel processors View full abstract»

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  • Hardware-based Packet Classification Made Fast and Efficient

    Page(s): 47 - 51
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (202 KB) |  | HTML iconHTML  

    To achieve fast packet classification, a hardware-based scheme, cross-producting recurrence (CPR), based on a formerly proposed cross-producting scheme is proposed. This scheme simplifies the classification procedure and decrease the distinct combinations of fields by hierarchically decomposing the multi-dimensional space. In the new scheme, the multi-dimensional space is endowed with a hierarchical property which self-divides into several smaller subspaces, whereas the procedure of packet classification is translated into repeatedly searching for matching subspaces. The required storage of the proposed scheme is significantly reduced since the distinct fields of subspaces is controlled by a pre-defined configuration and can be much less than that of the filters. The experimental results demonstrate the effectiveness and scalability of the proposed scheme View full abstract»

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  • Embedded Fingerprint Verification System

    Page(s): 52 - 57
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (282 KB) |  | HTML iconHTML  

    Fingerprint verification is one of the most reliable personal identification methods in biometrics. In this paper, an effective fingerprint verification system is presented. We describe an enhanced fingerprint verification system consisting of image pre-processing, feature extraction and matching processes. Improved image pre-processing and broken ridge reconnection methods are proposed. In this paper, we also describe the design and implementation of a fingerprint verification system on SoC View full abstract»

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  • SaNSO 2005 Foreword

    Page(s): xxvi
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  • SaNSO-2005 Program Committee

    Page(s): xxvii
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  • SaNSO-2005 Reviewers

    Page(s): xxviii
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  • Pulse Position Modulation for Active RFID System

    Page(s): 58 - 62
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (206 KB) |  | HTML iconHTML  

    Radio frequency identification (RFID) enables everyday objects to be identified, tracked, and recorded. This paper presents a design of N-ary pulse position modulation transmission-only active RFID system for monitoring of large number and high density objects. A burst frame from tag consists of multiple duplicated blink units and the interval between them is randomly selected from predefined interval steps to avoid continuous collision. The reader segments composite pulse streams and performs cross-correlation to recover the overlapped blink unit. The tag can be read in registration state or pattern matching state. Simulations show that the system is power efficient, large capacity, and fast reactive View full abstract»

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  • Novel Anti-collision Algorithms for Fast Object Identification in RFID System

    Page(s): 63 - 67
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (265 KB) |  | HTML iconHTML  

    We propose two ALOHA-based Dynamic Framed Slotted ALOHA algorithms (DFSA) using tag estimation method (TEM), which estimates the number of tags around the reader, and dynamic slot allocation (DSA), which dynamically allocates the frame size for the number of tags. We compare the performance of the proposed DFSA with the conventional Framed Slotted ALOHA algorithm (FSA) using simulation. According to the analysis, two proposed DFSA algorithms show better performance than FSA algorithm regardless of the number of tags View full abstract»

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  • A node-based available bandwidth evaluation in IEEE 802.11 ad hoc networks

    Page(s): 68 - 72
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    We propose a new technique to estimate the available bandwidth of wireless nodes and by extension of one-hop links in IEEE 802.11-based ad hoc networks. Our technique exploits the fact that a node can estimate the channel occupancy by monitoring its environment. It provides a non-intrusive estimation meaning that it doesn't generate additional traffic to perform the evaluation. We show by simulations that our technique provides an accurate estimation of available bandwidth on wireless links in mobile ad hoc environment View full abstract»

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  • More Efficient and Secure Remote User Authentication Scheme using Smart Cards

    Page(s): 73 - 77
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    In 2004, Lee et al. proposed an improvement to Chien et al's scheme to prevent parallel session attack and in which any legal users could choose and change their passwords freely. This paper, however, demonstrates that Lee et al.'s scheme is vulnerable to masquerading server attack. Additionally, we point out to the system's secret key forward secrecy problem and insecure password change. Furthermore, the current paper presents a more efficient and secure scheme in that it not only resolves such problems but also involves less computations and communications than Lee et al.'s scheme View full abstract»

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