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2005 International Conference on Computer Design

Date 2-5 Oct. 2005

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Displaying Results 1 - 25 of 119
  • Proceedings. 2005 International Conference on Computer Design

    Publication Year: 2005
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  • 2005 International Conference on Computer Design - Title Page

    Publication Year: 2005, Page(s):i - ii
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  • 2005 International Conference on Computer Design - Copyright

    Publication Year: 2005, Page(s): iv
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  • 2005 International Conference on Computer Design - Table of contents

    Publication Year: 2005, Page(s): v
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  • Welcome message

    Publication Year: 2005, Page(s): xiv
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  • Organizing Committee

    Publication Year: 2005, Page(s): xv
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  • Program Committee

    Publication Year: 2005, Page(s): xvi
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  • Additional reviewers

    Publication Year: 2005, Page(s): xviii
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  • Latency lags bandwidth

    Publication Year: 2005
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (57 KB) | HTML iconHTML

    Summary form only given. As I review performance trends, I am struck by a consistent theme across many technologies over many years: bandwidth improves much more quickly than latency for four different technologies: disks, networks, memories and processors. A rule of thumb to quantify the imbalance is: bandwidth improves by more than the square of the improvement in latency. This paper lists a hal... View full abstract»

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  • Temperature-dependent optimization of cache leakage power dissipation

    Publication Year: 2005, Page(s):7 - 12
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (280 KB) | HTML iconHTML

    Leakage power consists of an increasing portion of the total power consumption for modern IC designs. Due to the strong inter-dependency between leakage and temperature, it becomes imperative to consider the thermal effects while optimizing the leakage power. In this paper, we present a temperature-dependent optimization methodology for on-chip caches. By integrating fast yet accurate coupled ther... View full abstract»

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  • Architectural considerations for energy efficiency

    Publication Year: 2005, Page(s):13 - 16
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (240 KB) | HTML iconHTML

    The formal analysis of parallelism and pipelining is performed on an 8-bit add-compare-select element of a Viterbi decoder. The results are quantified through a study of the delay and energy behaviors of gates and complex circuits due to supply scaling and circuit optimization on a modified test setup accounting for routing cost. The energy-throughput relationships of both pipelining and paralleli... View full abstract»

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  • Reducing the latency and area cost of core swapping through shared helper engines

    Publication Year: 2005, Page(s):17 - 23
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB) | HTML iconHTML

    Technologies scaling trends and the limitations of packaging and cooling have intensified the need for thermally efficient architectures and architecture-level temperature management techniques. To combat these trends, we explore the use of core swapping on microcore architecture, a deeply decoupled processor core with larger structures factored out as helper engines. The microcore architecture pr... View full abstract»

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  • Analytical model for sensor placement on microprocessors

    Publication Year: 2005, Page(s):24 - 27
    Cited by:  Papers (12)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (184 KB) | HTML iconHTML

    Thermal management in microprocessors has become a major design challenge in recent years. Thermal monitoring through hardware sensors is important, and these sensors must be carefully placed on the chip to account for thermal gradients. In this paper, we present an analytical model that describes the maximum temperature differential between a hot spot and a region of interest based on their dista... View full abstract»

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  • Pre-layout physical connectivity prediction with application in clustering-based placement

    Publication Year: 2005, Page(s):31 - 37
    Cited by:  Papers (1)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (278 KB) | HTML iconHTML

    In this paper, we introduce a structural metric, logic contraction, for pre-layout physical connectivity prediction. For a given set of nodes forming a cluster in a netlist, we can predict their proximity in the final layout based on the logic contraction value of the cluster. We demonstrate a very good correlation of our pre-layout measure with the post-layout physical distances between those nod... View full abstract»

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  • Efficient rectilinear Steiner tree construction with rectilinear blockages

    Publication Year: 2005, Page(s):38 - 44
    Cited by:  Papers (28)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB) | HTML iconHTML

    Given n points on a plane, a rectilinear Steiner minimal tree (RSMT) connects these points through some extra points called Steiner points to achieve a tree with minimal total wire length. Taking blockages into account dramatically increases the problem complexity. It is extremely unlikely that an efficient optimal algorithm exists for rectilinear Steiner minimal tree construction with rectilinear... View full abstract»

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  • X-routing using two Manhattan route instances

    Publication Year: 2005, Page(s):45 - 50
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB) | HTML iconHTML

    In deep sub-micron (DSM) technologies, wire delays comprise a dominant fraction of the total delay of a design. As a consequence, routing techniques which reduce the total wire length of a design are highly relevant to such technologies. One such approach which holds promise is that of non-Manhattan routing (or X routing). In this paper, we describe a technique to perform non-Manhattan routing by ... View full abstract»

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  • Hardware support for bulk data movement in server platforms

    Publication Year: 2005, Page(s):53 - 60
    Cited by:  Papers (2)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (256 KB) | HTML iconHTML

    Bulk data movement occurs commonly in server work-loads and their performance is rather poor on today's microprocessors. We propose the use of small dedicated copy engines, and present a detailed analysis of a bulk data copy engine architecture. We describe the hardware support required to implement the copy engine and to tightly integrate it into server platforms. Our evaluation is based on an ex... View full abstract»

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  • Counter-based cache replacement algorithms

    Publication Year: 2005, Page(s):61 - 68
    Cited by:  Papers (9)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB) | HTML iconHTML

    Recent studies have shown that in highly associative caches, the performance gap between the least recently used (LRU) and the theoretical optimal replacement algorithms is large, suggesting that alternative replacement algorithms can improve the performance of the cache. One main reason for this performance gap is that in the LRU replacement algorithm, a line is only evicted after it becomes the ... View full abstract»

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  • Utilizing horizontal and vertical parallelism with a no-instruction-set compiler for custom datapaths

    Publication Year: 2005, Page(s):69 - 74
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB) | HTML iconHTML

    Performance of programs can be improved by utilizing their horizontal and vertical parallelism. In some processors (VLIW based), compiler can utilize horizontal parallelism by controlling the schedule of independent operations. Vertical parallelism is utilized through pipelining. However, in all processors, structure of pipeline is fixed and compiler has no control over it. In application-specific... View full abstract»

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  • Are today's verification tools able to handle current design challenges?

    Publication Year: 2005
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (58 KB) | HTML iconHTML

    Summary form only given. With the ever increasing growth of size and complexity of digital designs, tools have just kept pace. Design engineers bare the brunt of the problem. To make use of dynamic verification, designers invest as much or more time into their testbenches as they do in the design they are creating. For static or formal verification, large designs with complex state spaces have cha... View full abstract»

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  • Energy-efficient color approximation for digital LCD interfaces

    Publication Year: 2005, Page(s):81 - 86
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB) | HTML iconHTML

    The limited resolution capabilities of color displays, coupled with the limited perceptual resolution of the human eye have been exploited to reduce the actual number of colors that are simultaneously displayed. In this work, we propose a color approximation approach, orthogonal to traditional color simplification schemes done either in the frame buffer or in the LCD controller; that targets the r... View full abstract»

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  • Application-specific power-aware workload allocation for voltage scalable MPSoC platforms

    Publication Year: 2005, Page(s):87 - 93
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (624 KB) | HTML iconHTML

    In this paper, we address the problem of selecting the optimal number of processing cores and their operating voltage/frequency for a given workload, to minimize overall system power under application-dependent QoS constraints. Selecting the optimal system configuration is non-trivial, since it depends on task characteristics and system-level interaction effects among the cores. For this reason, o... View full abstract»

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  • LCD display energy reduction by user monitoring

    Publication Year: 2005, Page(s):94 - 97
    Cited by:  Papers (12)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (240 KB) | HTML iconHTML

    This paper introduces a new method to save energy of computer display. Unlike existing power management schemes, which link the display operation to a key press or movement of the mouse, we employ a video camera to bind the display power state to the actual user's attention. The proposed method keeps display active only if its user looks at the screen. When the user detracts his/her attention from... View full abstract»

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  • Frame buffer energy optimization by pixel prediction

    Publication Year: 2005, Page(s):98 - 101
    Cited by:  Papers (7)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (192 KB) | HTML iconHTML

    We propose a technique to reduce the energy consumption of the frame buffer memory, based on the spatial locality of images and display frames. Our scheme reduces energy by selectively avoiding reads from the frame buffer when identical adjacent pixels are detected. This is made possible by using an auxiliary memory that stores the locality information. The proposed architecture allows to dynamica... View full abstract»

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  • Energy and performance analysis of mapping parallel multi-threaded tasks for an on-chip multi-processor system

    Publication Year: 2005, Page(s):102 - 104
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (176 KB) | HTML iconHTML

    Multiprocessor systems offer superior performance and potentially better energy-reduction than single-processor systems. It all depends, however, on how well the application can be mapped onto the architecture. Indeed, a careful tradeoff of energy and performance requires a thorough understanding of the energy consumption pattern of the application across the architecture. We develop a simulation ... View full abstract»

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