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14th International Conference on Parallel Architectures and Compilation Techniques (PACT'05)

Date 17-21 Sept. 2005

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  • PACT 2005. 14th International Conference on Parallel Architectures and Compilation Techniques

    Publication Year: 2005
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  • 14th International Conference on Parallel Architectures and Compilation Techniques - Title Page

    Publication Year: 2005, Page(s):i - iii
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  • 14th Internatiionall Confference on Parallllell Archiittecttures and Compiillattiion Techniiques - Copyright Page

    Publication Year: 2005, Page(s): iv
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  • 14th Internatiionall Confference on Parallllell Archiittecttures and Compiillattiion Techniiques - Table of contents

    Publication Year: 2005, Page(s):v - viii
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  • Message from the General Chair

    Publication Year: 2005, Page(s): ix
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  • Message from the Program Chair

    Publication Year: 2005, Page(s): x
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  • Tutorials and Workshops

    Publication Year: 2005, Page(s): xi
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (23 KB) | HTML iconHTML

    Provides an abstract for each of the tutorial presentations and a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings. View full abstract»

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  • Committees

    Publication Year: 2005, Page(s):xii - xiii
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  • list-reviewer

    Publication Year: 2005, Page(s):xiv - xv
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  • Multi-core to the masses

    Publication Year: 2005
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (30 KB) | HTML iconHTML

    Summary form only given. It is likely that 2005 will be viewed as the year that parallelism came to the masses, with multiple vendors shipping dual/multi-core platforms into the mainstream consumer and enterprise markets. Assuming that this trend will follow Moore's Law scaling, mainstream systems will contain over 10 processing cores by the end of the decade, yielding unprecedented theoretical pe... View full abstract»

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  • Variational path profiling

    Publication Year: 2005, Page(s):7 - 16
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (234 KB) | HTML iconHTML

    Current profiling techniques are good at identifying where time is being spent during program execution. These techniques are not as good at pinpointing exactly where in the execution there are definite opportunities a programmer can exploit with optimization. In this paper we present a new type of profiling analysis called variational path profiling (VPP). VPP pinpoints exactly where in the progr... View full abstract»

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  • Extended whole program paths

    Publication Year: 2005, Page(s):17 - 26
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (216 KB) | HTML iconHTML

    We describe the design, generation and compression of the extended whole program path (eWPP) representation that not only captures the control flow history of a program execution but also its data dependence history. This representation is motivated by the observation that typically a significant fraction of data dependence history can be recovered from the control flow trace. To capture the remai... View full abstract»

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  • Instruction based memory distance analysis and its application to optimization

    Publication Year: 2005, Page(s):27 - 37
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2472 KB) | HTML iconHTML

    Feedback-directed optimization has become an increasingly important tool in designing and building optimizing compilers as it provides a means to analyze complex program behavior that is not possible using traditional static analysis. Feedback-directed optimization offers the compiler opportunities to analyze and optimize the memory behavior of programs even when traditional array-based analysis i... View full abstract»

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  • HPS: hybrid profiling support

    Publication Year: 2005, Page(s):38 - 47
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (216 KB) | HTML iconHTML

    Key to understanding and optimizing complex applications is our ability to dynamically monitor executing programs with low overhead and high accuracy. Toward this end, we present HPS, a hybrid profiling support system. HPS employs a hardware/software approach to program sampling that transparently, efficiently, and dynamically samples an executing instruction stream. Our system is an extension and... View full abstract»

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  • Maximizing CMP throughput with mediocre cores

    Publication Year: 2005, Page(s):51 - 62
    Cited by:  Papers (30)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (248 KB) | HTML iconHTML

    In this paper we compare the performance of area equivalent small, medium, and large-scale multithreaded chip multiprocessors (CMTs) using throughput-oriented applications. We use area models based on SPARC processors incorporating these architectural features. We examine CMTs with in-order scalar processor cores, 2-way or 4-way in-order superscalar cores, private primary instruction and data cach... View full abstract»

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  • Characterization of TCC on chip-multiprocessors

    Publication Year: 2005, Page(s):63 - 74
    Cited by:  Papers (14)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (272 KB) | HTML iconHTML

    Transactional coherence and consistency (TCC) is a novel coherence scheme for shared memory multiprocessors that uses programmer-defined transactions as the fundamental unit of parallel work, synchronization, coherence, and consistency. TCC has the potential to simplify parallel program development and optimization by providing a smooth transition from sequential to parallel programs. In this pape... View full abstract»

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  • Store-ordered streaming of shared memory

    Publication Year: 2005, Page(s):75 - 84
    Cited by:  Papers (5)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB) | HTML iconHTML

    Coherence misses in shared-memory multiprocessors account for a substantial fraction of execution time in many important scientific and commercial workloads. Memory streaming provides a promising solution to the coherence miss bottleneck because it improves memory level parallelism and lookahead while using on-chip resources efficiently. We observe that the order in which shared data are consumed ... View full abstract»

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  • An event-driven multithreaded dynamic optimization framework

    Publication Year: 2005, Page(s):87 - 98
    Cited by:  Papers (8)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (184 KB) | HTML iconHTML

    Dynamic optimization has the potential to adapt the program's behavior at run-time to deliver performance improvements over static optimization. Dynamic optimization systems usually perform their optimization in series with the application's execution. This incurs overhead which reduces the benefit of dynamic optimization, and prevents some aggressive optimizations from being performed. In this pa... View full abstract»

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  • Design and implementation of a compiler framework for helper threading on multi-core processors

    Publication Year: 2005, Page(s):99 - 109
    Cited by:  Papers (12)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (632 KB) | HTML iconHTML

    Helper threading is a technique that utilizes a second core or logical processor in a multi-threaded system to improve the performance of the main thread. A helper thread executes in parallel with the main thread that it attempts to accelerate. In this paper, the helper thread merely prefetches data into a shared cache and does not incur any other programmer visible effects. Helper thread prefetch... View full abstract»

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  • Compiler directed early register release

    Publication Year: 2005, Page(s):110 - 119
    Cited by:  Papers (8)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (248 KB) | HTML iconHTML

    This paper presents a novel compiler directed technique to reduce the register pressure and power of the register file by releasing registers early. The compiler identifies registers that mil only be read once and renames them to different logical registers. Upon issuing an instruction with one of these logical registers as a source, the processor knows that there will be no more uses of it and ca... View full abstract»

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  • Automatic selection of compiler options using non-parametric inferential statistics

    Publication Year: 2005, Page(s):123 - 132
    Cited by:  Papers (9)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (296 KB) | HTML iconHTML

    In this paper, we propose a statistical method to determine the setting of compiler options. Conventionally, programmers use standard - Ox settings which are provided by compiler developers. However, in order to obtain maximal performance, it is necessary to tune the compiler setting for the application as well as the underlying architecture. In this paper, we propose a methodology to configure co... View full abstract»

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  • Data-centric transformations on non-integer iteration spaces

    Publication Year: 2005, Page(s):133 - 142
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB) | HTML iconHTML

    Data-centric transformations have been used in recent years to improve locality for several classes of applications. However, the existing work has applied these transformations for integer iteration spaces, i.e., the iteration spaces involving loop variables that take integer values between specified lower and upper bounds. In many applications, a loop could involve a loop variable which takes va... View full abstract»

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  • Efficient techniques for advanced data dependence analysis

    Publication Year: 2005, Page(s):143 - 153
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (232 KB) | HTML iconHTML

    Scientific source code for high performance computers is extremely complex containing irregular control structures with complicated expressions. This complexity makes it difficult for compilers to analyze the code and perform optimizations. In particular with regard to program parallelization, complex expressions are often not taken intro consideration during the data dependence analysis phase. In... View full abstract»

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  • Parallel programming and parallel abstractions in Fortress

    Publication Year: 2005
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (32 KB)

    Summary form only given. The Programming Language Research Group at Sun Microsystems Laboratories seeks to apply lessons learned from the Java (TM) programming language to the next generation of programming languages. The Java language supports platform-independent parallel programming with explicit multithreading and explicit locks. As part of the DARPA program for High Productivity Computing Sys... View full abstract»

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  • Optimizing Compiler for the CELL Processor

    Publication Year: 2005, Page(s):161 - 172
    Cited by:  Papers (34)  |  Patents (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (272 KB) | HTML iconHTML

    Developed for multimedia and game applications, as well as other numerically intensive workloads, the CELL processor provides support both for highly parallel codes, which have high computation and memory requirements, and for scalar codes, which require fast response time and a full-featured programming environment. This first generation CELL processor implements on a single chip a Power Architec... View full abstract»

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