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13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)

18-20 April 2005

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Displaying Results 1 - 25 of 65
  • 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines - Cover

    Publication Year: 2005, Page(s): c1
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  • 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines - Title Page

    Publication Year: 2005, Page(s):i - iii
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  • 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines - Copyright Page

    Publication Year: 2005, Page(s): iv
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  • 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines - Table of contents

    Publication Year: 2005, Page(s):v - x
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  • Conference Organizers

    Publication Year: 2005, Page(s): xi
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  • Efficient hardware data mining with the Apriori algorithm on FPGAs

    Publication Year: 2005, Page(s):3 - 12
    Cited by:  Papers (37)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (264 KB) | HTML iconHTML

    The Apriori algorithm is a popular correlation-based data mining kernel. However, it is a computationally expensive algorithm and the running times can stretch up to days for large databases, as database sizes can extend to Gigabytes. Through the use of a new extension to the systolic array architecture, time required for processing can be significantly reduced. Our array architecture implementati... View full abstract»

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  • A novel 2D filter design methodology for heterogeneous devices

    Publication Year: 2005, Page(s):13 - 22
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (216 KB) | HTML iconHTML

    In many image processing applications, fast convolution of an image with a large 2D filter is required. Field programable gate arrays (FPGAs) are often used to achieve this goal due to their fine grain parallelism and reconfigurability. However, the heterogeneous nature of modern reconfigurable devices is not usually considered during design optimization. This paper proposes an algorithm that expl... View full abstract»

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  • Prototyping architectural support for program rollback using FPGAs

    Publication Year: 2005, Page(s):23 - 32
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (232 KB) | HTML iconHTML

    This paper presents a processor and memory-hierarchy prototype based on FPGAs that provides hardware support for program rollback. We use this prototype to demonstrate how compiler- or user-controlled speculative execution can help in debugging production codes. The system is based on a synthesizable VHDL implementation of a 32-bit processor compliant with the SPARC V8 architecture. We conduct exp... View full abstract»

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  • Register file architecture optimization in a coarse-grained reconfigurable architecture

    Publication Year: 2005, Page(s):35 - 44
    Cited by:  Papers (9)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (192 KB) | HTML iconHTML

    This paper investigates the impact of the local and global register file architecture on a reconfigurable system based on the ADRES architecture. The register files consume a significant amount of area on the reconfigurable device, and their architecture has a strong impact on the performance. We found that the global registers should be tightly connected to as many functional units as possible, w... View full abstract»

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  • Handling different computational granularity by a reconfigurable IC featuring embedded FPGAs and a network-on-chip

    Publication Year: 2005, Page(s):45 - 54
    Cited by:  Papers (3)  |  Patents (106)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (192 KB) | HTML iconHTML

    A system-on-chip integrating a microprocessor, three embedded FPGA (eFPGA) and an eight port network-on-chip (NoC) is implemented in a 90nm CMOS technology. The system has been designed to execute complex multimedia applications by the use of hardware accelerators mapped to a reconfigurable platform based on a message-passing architecture. Computational kernels are mapped as hardware autonomous pr... View full abstract»

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  • A study of the scalability of on-chip routing for just-in-time FPGA compilation

    Publication Year: 2005, Page(s):57 - 62
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (168 KB) | HTML iconHTML

    Just-in-time (JIT) compilation has been used in many applications to enable standard software binaries to execute on different underlying processor architectures. We previously introduced the concept of a standard hardware binary, using a just-in-time compiler to compile the hardware binary to a field-programmable gate array (FPGA). Our JIT compiler includes lean versions of technology mapping, pl... View full abstract»

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  • Simplifying the integration of processing elements in computing systems using a programmable controller

    Publication Year: 2005, Page(s):63 - 72
    Cited by:  Papers (12)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (232 KB) | HTML iconHTML

    As technology sizes decrease and die area increases, designers are creating increasingly complex computing systems using FPGAs. To reduce design time for new products, the reuse of previously designed intellectual property (IP) cores is essential. However, since no universally accepted interface standards exist for IP cores, there is often a certain amount of redesign necessary before they are inc... View full abstract»

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  • Evaluation of code generation strategies for scalar replaced codes in fine-grain configurable architectures

    Publication Year: 2005, Page(s):73 - 82
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB) | HTML iconHTML

    Fine-grain configurable architectures such as contemporary fieid-programmable gate-arrays (FPGAs) offer ample opportunities for data reuse through application-specific storage structures, making them an ideal target for memory-intensive image/signal processing computations. In this paper we explore the area and time trade-off in terms of configurable resources and overall wall-clock time of severa... View full abstract»

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  • FPGA particle graphics hardware

    Publication Year: 2005, Page(s):85 - 94
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (200 KB) | HTML iconHTML

    Particle graphics simulations are well suited for modeling phenomena such as water, cloth, explosions, fire, smoke, and clouds. They are normal realized in software, as pan of an interactive graphics application, such as a video game. Their use in such applications is limited by the computational burden and resource competition they create for a host application. We present the design of a hardwar... View full abstract»

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  • Reconfigurable designs for radiosity

    Publication Year: 2005, Page(s):95 - 104
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB) | HTML iconHTML

    We develop reconfigurable designs to support radiosity, a computer graphics algorithm for producing highly realistic images of artificial scenes, but which is computationally expensive. We implement radiosity using stochastic raytracing, which affords both instruction-level and data parallelism. Our designs are parameterisable by bitwidth, allowing trade-offs between image quality and computation ... View full abstract»

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  • Hardware factorization based on elliptic curve method

    Publication Year: 2005, Page(s):107 - 116
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (192 KB) | HTML iconHTML

    The security of the most popular asymmetric cryptographic scheme RSA depends on the hardness of factoring large numbers. The best known method for factorization large integers is the general number field sieve (GNFS). Recently, architectures for special purpose hardware for the GNFS have been proposed. One important step within the GNFS is the factorization of mid-size numbers for smoothness testi... View full abstract»

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  • Metropolitan road traffic simulation on FPGAs

    Publication Year: 2005, Page(s):117 - 126
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (184 KB) | HTML iconHTML

    This work demonstrates that road traffic simulation of entire metropolitan areas is possible with reconfigurable supercomputing that combines 64-bit microprocessors and FPGAs in a high bandwidth, low latency interconnect. Previously, traffic simulation on FPGAs was limited to very-short road segments or required a very large number of FPGAs. Our data streaming approach overcomes scaling issues ass... View full abstract»

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  • Time domain numerical simulation for transient waves on reconfigurable coprocessor platform

    Publication Year: 2005, Page(s):127 - 136
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB) | HTML iconHTML

    A successful application-oriented reconfigurable coprocessor design requires not only a powerful FPGA-based computing engine along with suitable hardware architecture, but also an efficient algorithm tailored for this special application. In this paper, we present our hardware architecture and numerical algorithms designed to speedup the time-domain finite-difference simulation of linear wave prop... View full abstract»

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  • COMA: a cooperative management scheme for energy efficient implementation of real-time operating systems on FPGA based soft processors

    Publication Year: 2005, Page(s):139 - 148
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (704 KB) | HTML iconHTML

    FPGA based soft processors are an attractive choice for implementing many embedded systems. As real-time operating systems are adopted in the development of many applications using soft processors, we propose COMA, a cooperative management scheme in this paper for energy efficient implementation of real-time operating systems on soft processors. By utilizing the configurability of soft processors,... View full abstract»

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  • An execution environment for reconfigurable computing

    Publication Year: 2005, Page(s):149 - 158
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (184 KB) | HTML iconHTML

    Although many studies have demonstrated the benefits of reconfigurable computing, it has not yet penetrated the mainstream. One of the biggest unsolved problems is the management of the reconfigurable hardware in a multi-threaded environment. Most research in reconfigurable computing has assumed a single-threaded model, but this is unrealistic for personal computing and many types of embedded comp... View full abstract»

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  • Higher radix floating-point representations for FPGA-based arithmetic

    Publication Year: 2005, Page(s):161 - 170
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB) | HTML iconHTML

    FPGA implementations of floating-point operators have historically been designed to use binary floating-point representations. The general computing world settled on binary floating-point representations over three decades ago, and more recently, the FPGA community followed their example. Binary representations were chosen to maximize numerical accuracy per bit of data, however, the unique nature ... View full abstract»

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  • An analysis of the double-precision floating-point FFT on FPGAs

    Publication Year: 2005, Page(s):171 - 180
    Cited by:  Papers (25)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (272 KB) | HTML iconHTML

    Advances in FPGA technology have led to dramatic improvements in double precision floating-point performance. Modern FPGAs boast several GigaFLOPs of raw computing power. Unfortunately, this computing power is distributed across 30 floating-point units with over 10 cycles of latency each. The user must find two orders of magnitude more parallelism than is typically exploited in a single microproce... View full abstract»

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  • A comparison of floating point and logarithmic number systems for FPGAs

    Publication Year: 2005, Page(s):181 - 190
    Cited by:  Papers (22)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (144 KB) | HTML iconHTML

    There have been many papers proposing the use of logarithmic numbers (LNS) as an alternative to floating point because of simpler multiplication, division and exponentiation computations. However, this advantage comes at the cost of complicated, inexact addition and subtraction, as well as the need to convert between the formats. In this work, we created a parameterized LNS library of computationa... View full abstract»

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  • Terrestrial-based radiation upsets: a cautionary tale

    Publication Year: 2005, Page(s):193 - 202
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (208 KB) | HTML iconHTML

    Problems with terrestrial-based neutron radiation from cosmic rays have become more commonplace. While the incident rate from neutron radiation is lower than space-based radiation, physics, system design and system locations have combined to make systems increasingly vulnerable to terrestrial radiation. FPGA systems are particularly sensitive to neutron radiation, as the FPGAs, microprocessors and... View full abstract»

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  • Automating the layout of reconfigurable subsystems using circuit generators

    Publication Year: 2005, Page(s):203 - 212
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB) | HTML iconHTML

    When designing systems-on-a-chip (SoCs), a unique opportunity exists to generate custom FPGA architectures that are specific to the application domain in which the device is used. The inclusion of such devices provides an efficient compromise between the flexibility of software and the performance of hardware, while at the same time allowing for post-fabrication modification of the SoC. To automat... View full abstract»

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