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VLSI Design and Video Technology, 2005. Proceedings of 2005 IEEE International Workshop on

Date 28-30 May 2005

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Displaying Results 1 - 25 of 140
  • A circuit macromodel of high voltage LDMOS based on numerical simulation

    Publication Year: 2005 , Page(s): 90 - 93
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (142 KB) |  | HTML iconHTML  

    Lateral double-diffused MOSFET (LDMOS) is widely used in power integrated circuits and microwave integrated circuits. So creating equivalent circuit of LDMOS is becoming more important. The previous models divided the on-state region of LDMOS into two parts, linear region and saturation region. The formulas and equivalent circuits are very complicated. This paper presents an I-V equation that is available in the whole on-state region by numerical simulation, and creates a macromodel of LDMOS circuits. The model contains fewer parameters that are easily extracted. Then we obtain a simpler equivalent circuit. Convergence becomes easier when using this equivalent circuit to simulate power integrated circuits. In the end, we give an application of our model. View full abstract»

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  • A method for classification of scenery documentary using MPEG-7 edge histogram descriptor

    Publication Year: 2005 , Page(s): 105 - 108
    Cited by:  Papers (4)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (192 KB) |  | HTML iconHTML  

    A double-threshold method is proposed to classify the scenery documentary using MPEG-7 edge histogram descriptor (EHD). The segments of a scenery documentary are classified into two categories, building and natural scenery clips, by global EHD of shot keyframes with the double-threshold method. Thus the basic semantic of shot can be extracted that describes the building or scenery. Furthermore the precision of EHD computing has been improved by enhancement and smoothing of the pictures and the results of classification are modified under the time constraint on shot keyframes. The experiments indicate that the accuracy of classification exceeds 90%. View full abstract»

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  • A multiple objective optimization based echo state network tree and application to intrusion detection

    Publication Year: 2005 , Page(s): 443 - 446
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (205 KB) |  | HTML iconHTML  

    Echo state network tree (ESNTree) is proposed in this paper. ESNTree changes the activation function of the hidden layer and modifies the initialization method of echo state network (ESN). If the number of input features is too large, genetic algorithm is used to extract better features. Thus the complexity of input feature space can be reduced. On the other hand, a divide-and-conquer method is used. Decision tree and ESN are combined to decrease the complexity of the classifier and make the classifier more comprehensible and more interpretable. Experiments show that ESNTree achieves better performance than neural network tree (NNTree). ESNTree has been applied to intrusion detection successfully. View full abstract»

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  • "Low-power VLSI design and implementation, from another point of view"

    Publication Year: 2005 , Page(s): xix
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  • The research on optimization techniques of 32-bit floating-point RISC microprocessor

    Publication Year: 2005 , Page(s): 63 - 66
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (207 KB) |  | HTML iconHTML  

    A high-performance low power dissipation 32-bit floating point RISC microprocessor XJ-1 has been successfully fabricated in 0.35 μm CMOS technology. A set of innovative optimization techniques are introduced for high performance operation, which include modified redundant Booth-3 algorithm for fast multiplication or division, dynamic SRAM mode control scheme for low power dissipation, embedded bus preselector improving the performance of bus interface, and the large capacity on-chip memory decreasing the amount of traffic with an external memory. These techniques improved the speed and quality with 38% boosted frequency and 39% reduced power dissipation. Each instruction and its random combinations have been tested, and the chip achieves 0.98 mA/MHz at 3.3 V power supply. View full abstract»

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  • Robust detection of brain function activity using blind signal separation

    Publication Year: 2005 , Page(s): 223 - 226
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (220 KB) |  | HTML iconHTML  

    Independent component analysis (ICA) is regarded as a useful technique for processing a wide range of practical signals, such as speech, radar and biomedical recordings. In the biomedical image processing, functional magnetic resonance imaging become a common tool for investigating the brain function and cognitive process. However, much debate on the preferred technique for analyzing these functional activation images is still a problem. In this contribution, blind signal separation via ICA is proposed to detect the brain function activities. Several experiment with digital image data were also carried out based on the presented fastICA algorithm. ICA technique is employed to separate the independent components of the observation and restrain the impact caused by the additive noise. The results using common method and ICA technique were also demonstrated and compared to show that the proposed ICA method significantly reduces the physiological baseline fluctuation and the background interfaces. View full abstract»

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  • "155Mb/s-40 Gb/s ICs for optic-fiber transmission systems"

    Publication Year: 2005 , Page(s): xx
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | PDF file iconPDF (33 KB)  
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  • Enhanced fast mode decision based on edge map and motion detail analysis for H.264/JVT

    Publication Year: 2005 , Page(s): 187 - 190
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (225 KB) |  | HTML iconHTML  

    The video coding standard H.264/JVT uses intra prediction and multi-block motion estimation to improve rate-distortion (RD) performance. However, full RD cost calculation for all intra-prediction modes and exhaustive searches for optimal motion vectors for all block sizes increases the computational complexity considerably with the number of prediction modes allowed. Wc propose an enhanced fast intra-prediction mode selection strategy based on edge mapping and a novel block segmentation approach to fast inter-prediction mode selection based on notion detail analysis, bearing in mind the full utilization of the already-available intermediate calculation results. Simulation results show that the proposed algorithms can efficiently reduce computational cost by about 43.3% and 84.7% respectively while maintaining similar visual quality and bit rate. View full abstract»

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  • Efficient parallel architecture for lifting-based two-dimensional discrete wavelet transform

    Publication Year: 2005 , Page(s): 75 - 78
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (172 KB) |  | HTML iconHTML  

    An efficient generic architecture for two-dimensional discrete wavelet transform (2-D DWT) with line-based method is proposed with using lifting scheme, in which the parallelism of four subbands transform in lifting-based 2-D DWT is exploited. The proposed architecture is designed to generate 4 subbands coefficients concurrently per clock cycle that :an perform a 1-level decomposition of a N×N image in approximately N2/4 working clock cycles, which has faster throughput rate but requires less hardware cost compared 10 the designs reported in previous literature. View full abstract»

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  • An easily reconfigurable simulation environment on FPGA based platform

    Publication Year: 2005 , Page(s): 71 - 74
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (223 KB) |  | HTML iconHTML  

    To speed up the media system-on-chip (SOC) design, a FPGA based platform is developed as a tool for the functional simulation. This platform can be easily reconfigurable as the simulation environment for a new SOC design. We propose a fast method to configure different simulation requirements on this platform. This method consists of two parts: one is a communication-centric framework for the simulation system mapped onto FPGA. The other is the establishment of the module library. While a modification should be made to the simulation requirements, the designer simply selects required modules from the library and their replaces the unneeded modules only with few alterations to the platform. So, the design speed can be accelerated. This fast method has been implemented to our media processor simulation platform MPSP-2 which is used to build the simulation environment for several media SOC designs. View full abstract»

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  • An ICA-based watermarking scheme resistant to copy attack

    Publication Year: 2005 , Page(s): 154 - 157
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (220 KB) |  | HTML iconHTML  

    As an attacking approach to digital watermark, copy attack has reduced the utility of watermark and posed a threat to copyright protection. In this paper, the image dependent signature is applied to mitigate this attack, which is embedded into the host image synchronously with the watermark. In the detection both signature and watermark can be extracted effectively through independent component analysis (ICA), a classical blind source separation (BSS) technique. By comparing this extracted signature with the one recalculated from the marked image, which describe the host image and the marked image respectively, the legality of the marked image can be identified. Thus the purpose of resisting copy attack can be realized. Simulation results demonstrate the robustness and validity of this proposed scheme. View full abstract»

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  • "Media processor and SoC"

    Publication Year: 2005 , Page(s): xxi - xxii
    Cited by:  Papers (1)
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  • Segmentation of players and team discrimination in soccer videos

    Publication Year: 2005 , Page(s): 369 - 372
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (200 KB) |  | HTML iconHTML  

    In this paper, we introduce methods to extract low-level features for soccer video analysis. A new method is proposed to segment players by using a mean distributed color feature. In order to discriminate which team the player belongs to, we use mutual chromatic correlation degree of players to identify team without extracting templates of players in advance. Experimental results are included to show the effectiveness of the method. View full abstract»

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  • "From hybrid video coding to advances in video transcoding"

    Publication Year: 2005 , Page(s): xiii
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  • Performance analysis of channel borrowing on hierarchical wireless networks

    Publication Year: 2005 , Page(s): 256 - 259
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (194 KB) |  | HTML iconHTML  

    Channel borrowing on hierarchical wireless networks is analyzed. A channel allocation strategy using both horizontal channel borrowing (HCB) and vertical channel borrowing (VCB) is presented and analyzed. Some simulation results are also given. From the simulation results, we can see, the proposed channel allocation strategy can reduce the blocking probability effectively. View full abstract»

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  • A high performance CMOS band-gap reference circuit design

    Publication Year: 2005 , Page(s): 32 - 35
    Cited by:  Papers (3)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (170 KB) |  | HTML iconHTML  

    This paper presents a CMOS band-gap reference design, which possesses the characteristics of low noise and high power supply rejection capability. Thus, it is suitable for the applications of a wide range of frequency and power input. In order to reduce thermal noise and to provide the output reference voltage that is resistant to power supply variations, the design incorporates an RC filter into conventional reference structure. Moreover, a fast turn-on circuit is introduced into the design to improve turn-on time of the circuit. The simulation results show that within the frequency range from 100 Hz to 10 MHz, the design has achieved an average power supply rejection ratio (PSRR) of more than 80 dB and an average noise of 8.5 μVrms. With the fast turn-on circuit, the improved band-gap reference circuit can reach its steady state within 100 microseconds. View full abstract»

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  • VLSI design of Ethernet CSMA/CD physical layer in HUB based on FSM/VHDL and its simulation

    Publication Year: 2005 , Page(s): 52 - 54
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (174 KB) |  | HTML iconHTML  

    In this paper, the physical layer of Ethernet CSMA/CD of HUB was designed with VHDL. The protocol of physical sub-layer of CSMA/CD was analyzed and the control circuits in HUB were designed with finite state machine (FSM). The whole system included port-controller, arbiter, clocks MUX, FIFO, core-controller and symbol generation and MUX. The functions of CSMA/CD were realized mainly by port-controller. Some parts of source programs were given out. The design was simulated in MAX+PLUS II tools under the clock frequency of 25 MHz. The simulated results demonstrate that the functions of physical sub-layer of CSMA/CD are realized. View full abstract»

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  • A 8-b 250-MS/S track-and-hold circuit in 0.18-μM CMOS

    Publication Year: 2005 , Page(s): 83 - 86
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (183 KB) |  | HTML iconHTML  

    This paper presents a novel design of a high-speed track-and-hold (T/H) circuit, featuring 8-b resolution up to 250 Ms/s and 100 MHz bandwidth. It is designed in a 0.18 μm CMOS process with a supply voltage of 1.8 Volt. The implemented input buffer allows a relatively large input range, 1 v-Vpp differential, and low harmonic distortion at the same time. A switched capacitor topology is used or the T/H circuit and amplifier is a folded cascode OTA with regulated cascode. In order to cancel the offset error between the inputs of an operational amplifier (OP-amp), a correlated double sampling (CDS) is used. The switches used are of transmission gate type. The circuit is supposed to work together with an embedded 250-Ms/s 150 mw 8-bit folding and interpolating CMOS ADC 0.18 μm. The track-and-hold consumes 7.7 mw. View full abstract»

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  • MediaSoC: a system-on-chip architecture for multimedia application

    Publication Year: 2005 , Page(s): 161 - 164
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (228 KB) |  | HTML iconHTML  

    The MediaSoC322IA consists of two fully programmable processor cores and integrates digital video encoder. The programmable cores toward a particular class of algorithms: the MediaDSP3200 for RISC/DSP oriented functions and multimedia processing, and the RISC3200 for bit stream processing and control function. Dedicated interface units for DRAM, SDRAM, Flash, SRAM, on screen display and the digital video encoder are connected via a 32-bit system bus with tie processor cores. The MediaSoC3221A is fabricated in a 0.18μm 6LM standard-cell SMIC CMOS technology, occupies about 20 mm2, and operates at 180 MHz. The MeidaSoC3221A are used to audio/video decoder for embedded multimedia application. View full abstract»

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  • Meaningful regions segmentation in CBIR

    Publication Year: 2005 , Page(s): 199 - 202
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (203 KB) |  | HTML iconHTML  

    In this paper, a new approach to fully automatic image segmentation is proposed to get the meaningful regions of general-purpose image. In order to avoid image over segmenting, the original input image is first smoothed by Gaussian filters with different scales. Then an improved ISODATA clustering algorithm with parameters selecting dynamically is proposed to cluster the image pixels into different regions. To eliminate those fragmentary regions, a region merging strategy is also presented. The final experimental results show that the proposed approach can effectively separate the objects from background of general-purpose image. View full abstract»

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  • Research on Lorenz chaotic stream cipher

    Publication Year: 2005 , Page(s): 431 - 434
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (190 KB) |  | HTML iconHTML  

    The chaotic signal, which possesses natural randomness, non-forecasting of orbit, sensitivity of initial state and controlling parameters, can be used for information encryption as sequence cipher. In this paper, a Lorenz chaotic stream cipher encryption algorithm is introduced, and then the natures of the algorithm have been analyzed. Finally, based on chaotic cipher theory and its application, simulation results are given. View full abstract»

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  • "Dataflow-based design methodology for dsp soc systems"

    Publication Year: 2005 , Page(s): xvii
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  • "Superresolution from multiple image frames"

    Publication Year: 2005 , Page(s): xvi
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  • An early warning model for risk management of securities based on the error inverse propagation neural network

    Publication Year: 2005 , Page(s): 393 - 396
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (239 KB) |  | HTML iconHTML  

    This paper has carried on the tentative discussion to the early warning model for risk management under the separation of the sectors of investment bank. The characteristic of the investment bank is analysed at first, then discern the risk of the investment bank to classify. The index system of early warning model is proposed. Propagating against error neural network of neural network theory is introduced. This network is utilised to build early warning model and realize the corresponding algorithm by the tool MATLAB. The theory and realistic meaning of this paper is to promote the development of investment bank theory of our country, opening up the research range of the financial theory, especially there are important theory meaning and applying value to the setting-up of the early warning system of risk of the securities business. View full abstract»

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  • Audio power amplifier using in cellular phone with improved PSRR

    Publication Year: 2005 , Page(s): 87 - 89
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (101 KB) |  | HTML iconHTML  

    A fully differential folded-cascode op-amp is applied into the audio power amplifier successfully. PSRR (power supply rejection ratio) of whole chip is higher than 60 dB between 20 Hz and 20 kHz, especially 82 dB at 217 Hz. Analysis and simulation has shown that PSRR of both op-amp and whole chip are improved. As a result, improved PSRR reduces the effect of noise on power supply lines being picked up and intensified by the audio power amplifier using cellular phone. The chip is manufactured by CSMC 0.6μm, 3.3 V/5 V, 2P2M, CMOS process. View full abstract»

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