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Memory Technology, Design, and Testing, 2005. MTDT 2005. 2005 IEEE International Workshop on

Date 3-5 Aug. 2005

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Displaying Results 1 - 25 of 37
  • 2005 IEEE International Workshop on Memory Technology, Design, and Testing - Cover

    Publication Year: 2005 , Page(s): c1
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  • 2005 IEEE International Workshop on Memory Technology, Design and Testing

    Publication Year: 2005
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  • 2005 IEEE International Workshop on Memory Technology, Design, and Testing - Copyright Page

    Publication Year: 2005 , Page(s): iv
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  • 2005 IEEE International Workshop on Memory Technology, Design, and Testing - Table of contents

    Publication Year: 2005 , Page(s): v - vii
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  • Foreword

    Publication Year: 2005 , Page(s): viii
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  • Organizing Committee

    Publication Year: 2005 , Page(s): ix
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  • Program Committee

    Publication Year: 2005 , Page(s): x
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  • list-reviewer

    Publication Year: 2005 , Page(s): xi
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  • Test Technology Technical Council

    Publication Year: 2005 , Page(s): xii - xiv
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  • Advanced simulation technology and its application in memory design and verification

    Publication Year: 2005 , Page(s): xv - xx
    Cited by:  Papers (1)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (252 KB) |  | HTML iconHTML  

    The simulation of memory circuits has been a challenge for analog simulators due to the requirement of handling high capacity and providing SPICE-like accuracy at the same time. New hierarchical isomorphic simulation technology was developed enabling the accurate simulation of nearly unlimited memory designs without performance penalty. The main technology concept is the compression of memory and computation for isomorphic subcircuits, which eliminates the need for cutting down designs to fit them into conventional simulation tools. With the arrival of nanometer technology the analysis of parasitic effects has become critical in verifying design functionality, timings, and power. This requires simulation tools not only to handle very large memories but also to analyze the effect of hundreds of million of parasitic elements. Several postlayout simulation flows are discussed and state-of-the-art RC reduction technology is introduced. View full abstract»

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  • Zero capacitor embedded memory technology for system on chip

    Publication Year: 2005 , Page(s): xxi - xxv
    Cited by:  Papers (2)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (338 KB) |  | HTML iconHTML  

    By harnessing the floating body (FB) effect of silicon on insulator devices, the authors introduced a true capacitor-less, single transistor DRAM - named Z-RAMtrade (zero capacitance DRAM) - which is capable of doubling memory density when compared to existing embedded DRAM technology (and achieving five times the density of current embedded SRAM), yet requires no exotic materials, no extra mask steps and no new physics. As no capacitor is required, the Z-RAM cell can readily be scaled as far as the transistor. The technology's bit-cell scalability was demonstrated at the 45nm node. It is easily envisaged that Z-RAM technology will scale well to at least the 22nm process node and ISi has already measured suitable characteristics in the FinFET transistors that may well be used at that time View full abstract»

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  • Novel self-convergent scheme logic-process-based multilevel/analog EEPROM memory

    Publication Year: 2005 , Page(s): 3 - 8
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (185 KB) |  | HTML iconHTML  

    A novel multilevel/analog electrically erasable programmable read only memory (EEPROM) cell fabricated by standard complementary metal oxide semiconductor (CMOS) logic process is presented. The cell is operated by select-gate-controlled channel current induced drain avalanche hot hole for programming and hot electron for erasing. The self-convergent programming scheme is proposed allows this cell to be easily adopted for the multilevel or analog storage. In addition, a compact SPICE sub-circuit model of the cell has been established to facilitate cell behavior simulation with its interfacing circuits, especially for multilevel/analog nonvolatile memory applications. View full abstract»

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  • A novel CMOS compatible embedded nonvolatile memory with zero process adder

    Publication Year: 2005 , Page(s): 9 - 12
    Cited by:  Papers (2)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (374 KB) |  | HTML iconHTML  

    We demonstrate a CMOS compatible reprogrammable nonvolatile memory cell using a regular n-channel MOSFET with under-lapped source/drain diffusions that requires no extra processing steps in a standard 130nm CMOS logic technology. Experimental results indicate good endurance and retention characteristics. A strategy for optimizing programming efficiency is identified with the addition of one extra mask to introduce drain optimization implants. View full abstract»

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  • Embedded OTP fuse in CMOS logic process

    Publication Year: 2005 , Page(s): 13 - 15
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (86 KB) |  | HTML iconHTML  

    This paper presents the embedded OTP fuse in standard CMOS logic compatible process without additional mask. The embedded OTP fuse can be programmed in 100μs per byte and be accessed in 6ns for 32 bits at once. The 32-bit OTP fuse takes less than 0.0085mm 2 in 0.25μm CMOS process and has 10-year data retention at 85°C. View full abstract»

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  • Via-programmable read-only memory design for full code coverage using a dynamic bit-line shielding technique

    Publication Year: 2005 , Page(s): 16 - 21
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (143 KB) |  | HTML iconHTML  

    Crosstalk between bit lines leads to read-1 failure in a high-speed via-programmable read only memory (ROM) and limits the coverage of applicable code patterns. Due to the fluctuations in bit-line intrinsic and coupling capacitances, the amount of noise coupled to a selected bit line may vary, resulting in the reduction of sensing margin. In this paper, we propose a dynamic bit-line shielding (DBS) technique, suitable to be implemented in compliable ROM, to eliminate the crosstalk-induced read failure and to achieve full code coverage. Experiments of the 256Kb instances with and without the DBS circuit were undertaken using 0.25μm and 0.18μm standard CMOS processes. The test results demonstrate the read-1 failures and confirm that the DBS technique can remove them successfully, allowing the ROM to operate under a wide range of supply voltage. View full abstract»

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  • A nor-type MLC ROM with novel sensing scheme for embedded applications

    Publication Year: 2005 , Page(s): 22 - 25
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (560 KB) |  | HTML iconHTML  

    3 bits per cell nor-type MLC ROM, multi layer cell read only memory macro of 4M bits density is presented. The MLC ROM is designed by a 0.18 μm CMOS logic process. The ROM cell of 0.80μm × 0.90μm with 0.05μm per step of the channel width and channel length increase is determined to obtain 16 levels of Ids. A scheme of 2-step sensing with current-to-voltage converter (step1) and an ADC (step2) are applied to obtain an access time of 10 ns. View full abstract»

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  • Dielectric tunnel parameters of CoFe/Al-O/CoFe in MTJ for 1T1MTJ MRAM applications

    Publication Year: 2005 , Page(s): 29 - 34
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (473 KB) |  | HTML iconHTML  

    Dielectric tunnel parameters of thin insulating layer in MTJ of MRAM cell are measured and analyzed. General mathematical derivations for dielectric tunnel parameters in bright and dark region of MTJ cell are derived. Dielectric tunnel offset voltage in bright region of MTJ may relate to the screening effect of uneven dipole charge layer by external ramping bias and the spin-accumulated magnetization dipole layer by nonlinear tunnel current. The symmetry variation of dielectric tunnel charge in dark region of MTJ demonstrates a good balanced charge-conserved ferromagnetic plate capacitor. Parameters extraction and equivalent circuit model of dielectric tunnel capacitance C and resistance R from current-voltage curve for data 0 and 1 during 1T1MTJ read mode are illustrated. View full abstract»

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  • A novel single poly-silicon EEPROM using trench floating gate

    Publication Year: 2005 , Page(s): 35 - 37
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (304 KB) |  | HTML iconHTML  

    A single poly-silicon trench gate-type EEPROM, SPTG, featuring low voltage operation and fast programming is proposed. Using a trench floating gate instead of the stack gate structure, this cell is suitable for embedded application. The trenched floating gate (FG) combining with a deep-N-well implanted region guarantees high coupling ratio for CHEI programming and source side FN erasing operation. This cell array in a NOR-type array features fast random access capacity and IIF 2 cell size. View full abstract»

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  • An investigation into three-level ferroelectric memory

    Publication Year: 2005 , Page(s): 38 - 43
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (208 KB) |  | HTML iconHTML  

    Ferroelectric random-access memory (FeRAM) is an emerging nonvolatile memory technology that has several key advantages over flash memory, including much greater program-erase endurance and much faster write speed. However, FeRAM array storage capacities currently lag behind those of flash memory by more than three orders of magnitude; consequently, FeRAM has so far tended to be used only in niche applications, such as smart cards and electronic metering. Significant increases in FeRAM storage density requires progress on many technical fronts. Most digital memory technologies use two possible data signal levels to encode one bit per storage cell. Multilevel cell flash memory uses four data signal levels to increase the storage density to two bits per cell. In this paper we report the results of a preliminary study that investigated the possibility of using three data signal levels to increase the array storage density from 1 bit per cell to an average of 1.5 bits per cell. The principal challenge is to ensure the accurate writing of the three signal states (ferroelectric film polarized in the "up" and "down" directions, and a depolarized film) and the reliable sensing of cell states in the presence of noise and inevitable device parameter variations. View full abstract»

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  • A 1GHz embedded DRAM macro and fully programmable BIST with at-speed bitmap capability

    Publication Year: 2005 , Page(s): 47 - 51
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (865 KB) |  | HTML iconHTML  

    A 1GHz 2Mb embedded DRAM macro and an associated fully programmable BIST block have been designed in a 90nm logic based technology. The DRAM macro has 128-bit I/O, sixteen banks, 1 ns interleaved operation, 4ns random access read pipeline, and an early write scheme. The BIST is used for at-speed testing of the DRAM macro and can accumulate fail data for redundancy repair and bitmap generation. It can be cascaded and shared between memory macrocells. View full abstract»

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  • A high speed BIST architecture for DDR-SDRAM testing

    Publication Year: 2005 , Page(s): 52 - 57
    Cited by:  Papers (3)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (173 KB) |  | HTML iconHTML  

    In this paper, we propose a high speed built-in self-test (BIST) design which can support the at-speed testing for DDR or DDR2 SDRAM. We use the pipeline strategy together with several special design techniques to achieve the high speed requirement. A scheme is developed which can efficiently solve the problem of different execution cycles of DDR or DDR2 SDRAM's commands and can generate a compact test sequence for the desired March algorithm(s). Our BIST can support single or multiple March algorithms. With the single algorithm design extremely high speed around 833 MHz is achieved using the TSMC 0.18μm technology. For the multiple-algorithms design, our design can still satisfy the speed requirement of DDR2 memory even with the 3 most complex March algorithms. Our experiment also shows that if only DDR memory testing is required, then more than 30 March algorithms can be integrated into our BIST design. View full abstract»

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  • A programmable built-in self-test for embedded DRAMs

    Publication Year: 2005 , Page(s): 58 - 63
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (966 KB) |  | HTML iconHTML  

    A memory test algorithm for detecting neighborhood pattern sensitive faults (NPSFs), including static NPSF (SNPSF), passive NPSF (PNPSF) and active NPSF (ANPSF), is proposed in this paper. The patterns can also detect all the traditional faults present in the memory array such as stuck-at faults (SAFs), transition faults (TFs), coupling faults (CFs) and address decoder faults. Next, a built-in self-test (BIST) architecture is proposed with low area overhead. The test pattern generator (TPG) for generating all patterns for NPSFs is implemented with on-chip cellular automata (CA) based circuit. View full abstract»

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  • Full-speed field programmable memory BIST supporting multi-level looping

    Publication Year: 2005 , Page(s): 67 - 71
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (82 KB) |  | HTML iconHTML  

    A full-speed field-programmable memory BIST controller is proposed. The proposed instruction and architecture designs enable full-speed operation of algorithms containing more than one level of looping. View full abstract»

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  • FSM-based programmable memory BIST with macro command

    Publication Year: 2005 , Page(s): 72 - 77
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (363 KB) |  | HTML iconHTML  

    We propose a structured design methodology to construct FSM-based programmable memory BIST. The proposed BIST can be programmed on-line, with a "macro command", to select a test algorithm from a predetermined set of algorithms that are built in the memory BIST. In general, there are a variety of heterogeneous memory modules in SOC, and it is not possible to test all of them with a single algorithm. Thus, the proposed scheme greatly simplifies the testing process. Besides, the proposed is more efficient in terms of circuit size and test data to be applied, and it requires less time to configure the BIST. We also develop a programmable memory BIST generator that automatically produces RTL model of the proposed BIST architecture for a given set of test algorithms. Experimental results show that the proposed method achieves a good flexibility with smaller circuit size compared with previous methods. View full abstract»

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  • DFT architecture for a dynamic fault model of the embedded mask ROM of SOC

    Publication Year: 2005 , Page(s): 78 - 82
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (160 KB) |  | HTML iconHTML  

    This paper describes a fail situation in the mass product testing of the embedded NAND-type mask ROM of a SOC "of passing in the high speed test, but fails in the low speed test", and propose a fault model of the situation. We also propose a general solution of testing to cope with this fault model. Finally, we invent DFT architecture to cover the fault model to reduce the testing time. View full abstract»

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