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Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors

10-12 Oct. 1994

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Displaying Results 1 - 25 of 117
  • Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors

    Publication Year: 1994
    Request permission for commercial reuse | PDF file iconPDF (98 KB)
    Freely Available from IEEE
  • On-chip TEC-QED ECC for ultra-large, single-chip memory systems

    Publication Year: 1994, Page(s):132 - 137
    Cited by:  Papers (4)  |  Patents (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (448 KB)

    Soft errors resulted from alpha-particle strikes are one of the major factors that reduces the reliability of memory chips. One way to improve reliability of the memory chip is to employ an on-chip code (ECC). This paper presents a triple-error correcting and quadruple-error detecting (TEC-QED) code that is capable of correcting three and detecting four soft errors simultaneously. Its design is ba... View full abstract»

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  • Design of TSC code-disjoint inverter-free PLA's for separable unordered codes

    Publication Year: 1994, Page(s):128 - 131
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (340 KB)

    This paper considers design of totally self-checking (TSC) code-disjoint (CD) PLA's under fault model which covers three classes of typical PLA faults. The inputs of a PLA are encoded with a separable unordered code and any PLA is inverter-free, which guarantees that it is crosspoint-irredundant and no bridging fault may cause undetected errors. The new optimal separable unordered codes are constr... View full abstract»

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  • Concurrent error detection in high speed carry-free division using alternative input data

    Publication Year: 1994, Page(s):124 - 127
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    Rapid advancements in technology demand innovative computation algorithms and hardware structures to achieve high performance. High speed dividers are commonly designed using SRT division methods. Recently, a high speed carry-free divider design using redundant binary representation has been presented. Based on the carry-free division algorithm and a more general cell fault mode instead of stuck-a... View full abstract»

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  • Architecture oriented logic optimization for lookup table based FPGAs

    Publication Year: 1994, Page(s):26 - 29
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (356 KB)

    A logic optimization criterion for lookup-table based field programmable gate arrays (FPGAs) is presented. Based on this criterion, several key operations of logic optimization, such as extraction, decomposition, resubstitution and simplification, are discussed, so as to make them evaluate the circuit cost in accordance with the target technology. Using our approaches to do logic optimization for ... View full abstract»

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  • Capturing synchronization specifications for sequential compositions

    Publication Year: 1994, Page(s):117 - 121
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    We explore the problem of adding synchronization information to high-level system specifications. At this level of specification the components of a system may follow non-trivial, but implicitly specified sequential protocol in order to perform their operations. We illustrate a method of extracting protocols for closely coupled systems of such components. A language is defined for specifying exter... View full abstract»

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  • Techniques for fast CMOS-based conditional sum adders

    Publication Year: 1994, Page(s):626 - 635
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (592 KB)

    Conditional sum adders, CSAs, and carry-lookahead adders, CLAs, both have logarithmic gate depth. However, CLAs require a final add stage while CSAs produce the sum bits in parallel with the final carry bit. For CMOS implementations, the depth advantage of CSA has been difficult to exploit since the traditional structure of CSAs have some heavily loaded internal nodes. We show that the CSA-operati... View full abstract»

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  • A class of good characteristic polynomials for LFSR test pattern generators

    Publication Year: 1994, Page(s):292 - 295
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    Linear Feedback Shift Registers (LFSRs) constitute a very efficient mechanism for generating pseudo-exhaustive or pseudo-random test sets for the built-in self-testing of digital circuits. However, a well-known problem with the use of LFSRs is the occurrence of linear dependencies in the generated patterns. In this paper, we show for the first time that the amount of linear dependencies can be con... View full abstract»

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  • Thermal design of an advanced multichip module for a RISC processor

    Publication Year: 1994, Page(s):608 - 611
    Cited by:  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB)

    Multichip module (MCM) technology is attracting attention from designers who need high-speed interchip connections and a reliable package for their circuit applications. This technology is being applied to realize a 1-ns cycle time 32-bit RISC processor, using 50 GHz AlGaAs/GaAs heterojunction bipolar transistor (HBT) technology and triple-level full-differential current mode logic (CML), at Renss... View full abstract»

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  • Grammar-based optimization of synthesis scenarios

    Publication Year: 1994, Page(s):20 - 25
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (496 KB)

    Systems for multi-level logic optimization are usually based on a set of specialized, loosely-related transformations which work on a network representation. The sequence of transformations in a synthesis scenario (script) is crucial for the performance of the whole system. This paper presents the application of a genetic algorithm for automatic tuning of scenarios, and therefore an approach for o... View full abstract»

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  • Tradeoffs in canonical sequential function representations

    Publication Year: 1994, Page(s):111 - 116
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (576 KB)

    State space exploration is of prime importance in the study of finite state sequential systems, with several efforts aimed at compact representation of the state space in order to tackle the state explosion problem. In the work presented on formal verification of inductively-defined hardware, we have identified a useful class of Boolean functions called linearly inductive functions (LIFs). We expl... View full abstract»

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  • Synchronization of wave-pipelined circuits

    Publication Year: 1994, Page(s):164 - 167
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB)

    We investigate the synchronization schemes of wave-pipelined circuits. Previous analysis of valid clocking in wave-pipelined circuits is discussed and an intentional clock skew is introduced between the input and output registers as a function of the timing parameters of the wave-pipelined circuit, registers, and clock period. It is shown that, a clock skew value can be determined from the circuit... View full abstract»

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  • Asymptotic limits of video signal processing architectures

    Publication Year: 1994, Page(s):622 - 625
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (296 KB)

    This paper investigates the effects of technology scaling on video signal processing (VSP) architectures. We evaluate the processor, the memory, and the interconnect delays using RC models and study how the response times of these logic components scale with feature size. Architectural parameters such as clock skew, clock frequency, memory interleaving, memory efficiency, and average waiting times... View full abstract»

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  • WRAPTure: a tool for evaluation and optimization of weights for weighted random pattern testing

    Publication Year: 1994, Page(s):288 - 290
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    Two problems in weighted random pattern testing are addressed: 1) finding the expected test length to sample all patterns in a given test set for a given weight set; and 2) finding the optimal weight set for minimizing expected test length for a given test set. Exact analytical expressions for expected test length for sampling all patterns from a test set are given. Expressions for approximating t... View full abstract»

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  • Peephole optimization of asynchronous macromodule networks

    Publication Year: 1994, Page(s):442 - 446
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB)

    Most high level synthesis tools for asynchronous circuits take descriptions in concurrent hardware description languages and generate networks of macromodules or handshake components. In this paper we describe a peephole optimizer for such macromodule networks that often effects area and/or time improvements. Our optimizer first deduces an equivalent black-box behavior for the given network of mac... View full abstract»

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  • Improved techniques for MCM layer assignment

    Publication Year: 1994, Page(s):604 - 607
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB)

    Studies the layer assignment problem of multi-chip modules (MMCs) and presents algorithms for layer assignment of 2-terminal and multiterminal nets. Solutions obtained by our experimental results show a significant reduction in the number of plane-pairs required by our algorithms, in comparison with the previous algorithms. We improve the upper bound for multiterminal nets and show that the soluti... View full abstract»

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  • Emerging technologies for electronic design and test

    Publication Year: 1994
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (88 KB)

    The need for tight coupling between methodologies for design-and-test, VLSI technology, architecture and CAD has never been as strong as it is today. The design and test challenges of today are due to the sudden demand for systems that deal with multimedia, high speed networking and computing, and wireless communications, to name a few. The competitive nature of these businesses puts enormous pres... View full abstract»

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  • Write buffer design for on-chip cache

    Publication Year: 1994, Page(s):311 - 316
    Cited by:  Papers (8)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (460 KB)

    Write strategy is an important part of cache design. The buffering scheme is frequently used to reduce the overhead associated with write operations. Although it is a common feature in cache design, there is no quantitative analysis on the effect of the write buffer. This study investigates the impact of the write buffer, particularly on a small on-chip cache. Five configurations, including write-... View full abstract»

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  • A VLSI chip for template matching

    Publication Year: 1994, Page(s):542 - 545
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB)

    We describe the design and implementation of a VLSI chip for image template matching. The hardware algorithm and architecture for template matching are based on a technique known as moment preserving pattern matching. The architecture fully utilizes the principles of parallelism and pipelining in order to obtain high speed and throughput. The proposed VLSI system is much simpler, achieves higher s... View full abstract»

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  • In the driver's seat of BooleDozer

    Publication Year: 1994, Page(s):518 - 521
    Cited by:  Papers (9)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB)

    The paper describes some of the synthesis controls in the BooleDozer synthesis system which are unique in concept and implementation. Rather than attempting to achieve the maximum amount of optimization in the minimum amount of run time, the designer specifies the restructuring level which allows him to specify to what extent the original structure should be preserved. We also describe controls wh... View full abstract»

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  • OFDD based minimization of fixed polarity Reed-Muller expressions using hybrid genetic algorithms

    Publication Year: 1994, Page(s):106 - 110
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    We present an ordered functional decision diagram (OFDD) based method to minimize fixed polarity Reed-Muller expressions (FPRMs) for very large functions using genetic algorithms (GAs). R. Dreschsler et al. (1994) presented fast heuristic methods for FPRM minimization and compared them to several other approaches. We show that better results for large functions can be obtained if these heuristics ... View full abstract»

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  • Short destabilizing paths in timing verification

    Publication Year: 1994, Page(s):160 - 163
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB)

    Designing an optimal clocking scheme for a sequential circuit requires accurate knowledge of the delay of its longest sensitizable and of its shortest destabilizing path. However, there is a large imbalance in the research effort spent on both types of paths. This paper tries to compensate this imbalance, by presenting a new destabilizing criterion, for which it will be proved that it leads to cor... View full abstract»

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  • Compression of embedded system programs

    Publication Year: 1994, Page(s):270 - 277
    Cited by:  Papers (34)  |  Patents (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (672 KB)

    Embedded systems are often sensitive to space, weight, and cost considerations. Reducing the size of stored programs can significantly improve these factors. This paper discusses a program compression methodology based on existing processor architectures. The authors examine practical and theoretical measures for the maximum compression rate of a suite of programs across six modern architectures. ... View full abstract»

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  • The effects of compiler options on application performance

    Publication Year: 1994, Page(s):340 - 343
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    Compiler optimizations play a pivotal role in determining the run-time performance of an application. Performance improvements stem from path length reduction, efficient instruction selection, pipeline scheduling, and memory penalty minimization. This paper describes typical optimizations and highlights the mechanisms by which they improve performance. We categorize the described optimizations as ... View full abstract»

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  • The PowerPC 604 microprocessor design methodology

    Publication Year: 1994, Page(s):404 - 408
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    The PowerPC 604 microprocessor design methodology represents an interesting evolution from the one used to produce the PowerPC 601 μP. While the PowerPC 601 μP was intended to provide a marketable PowerPC product as quickly as possible, the PowerPC 604 μP had a higher performance implementation goal. We feel that our design techniques were appropriate for this new balance of schedule and ... View full abstract»

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