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IEEE-NEWCAS Conference, 2005. The 3rd International

Date 19-22 June 2005

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Displaying Results 1 - 25 of 102
  • State assignment for low-leakage finite state machines

    Publication Year: 2005 , Page(s): 115 - 118
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (173 KB) |  | HTML iconHTML  

    The problem of minimizing both static and dynamic power of synchronous circuits in explored in this paper. We present a new cost function for evaluating the static leakage in finite state machines. New techniques for low leakage (static) and low power (dynamic) state assignment are considered. We show that there are 2n state assignments having equal dynamic cost and a different static cost. These techniques were applied to MCNC benchmark circuits and results are given. View full abstract»

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  • A low-power driving scheme for a-Si:H active-matrix organic light-emitting diode displays

    Publication Year: 2005 , Page(s): 119 - 122
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (312 KB) |  | HTML iconHTML  

    This paper describes a low-power driving scheme along with a pixel circuit based on hydrogenated amorphous silicon (a-Si:H) technology for active matrix organic light emitting diode (AMOLED) displays. The driving scheme can provide different current levels for the OLED while compensating for long-term (and gradual) instabilities caused by material defect metastability which will make it amenable for use in AMOLED displays. Moreover, since the threshold voltage is known in this method, it can be used to compensate for the time-dependent errors of the charge injection and clock feed-through effects. Therefore, the error for a 3V shift in the VT of T1 is almost zero. More importantly, it has low power consumption because the line capacitance is charged just one time during the programming cycle. For example, the total power consumption of a QVGA array (240*320) is expected to be less than 1.5W. View full abstract»

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  • A low-voltage low-noise CMOS instrumentation amplifier for portable medical monitoring systems

    Publication Year: 2005 , Page(s): 295 - 298
    Cited by:  Papers (6)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (406 KB) |  | HTML iconHTML  

    This paper presents a low voltage low noise CMOS instrumentation amplifier (IA) suitable for portable health monitoring devices such as electrocardiogram (ECG) and electroencephalogram (EEG). Based on a current-mode topology, the IA is able to operate under a 1-V supply and consumes 50 μW while providing a voltage gain of 150. An optimum trade-off between noise and voltage headroom is obtained by choosing appropriate operating points and sizes of transistors. The measured input referred noise integrated from 0.4Hz to 200Hz is 1.27 μVrms. The current-mode DC rejection circuit can suppress up to ±11 mV of input DC pedestal caused by medical electrodes, as well as the DC offset of the IA. The IA is fabricated in a standard 0.35μm CMOS technology with a core chip area of 0.7mm2. View full abstract»

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  • A 1-mW 2-GHz Q-enhanced LC bandpass filter for low-power RF applications

    Publication Year: 2005 , Page(s): 365 - 368
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (238 KB) |  | HTML iconHTML  

    A low-power tunable LC bandpass filter is introduced for radio-frequencies applications. Center frequency of the filter can be tuned over a range of 144 MHz around 2 GHz at high quality factor (Q). Input signal is given to the LC resonator by an on-chip transformer, which reduces the power-consumption to 1 mW at a Q of 81. The Q-factor can also be tuned up to 150 when the center frequency remains at 2 GHz. Dynamic range of the filter is more than 50 dB with 1.2 V supply voltage. Modeling of the proposed filter and simulation results produced using IBM CMOS8RF 0.13 mum technology are presented View full abstract»

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  • Implementation and error performance evaluation of an iterative decoding algorithm

    Publication Year: 2005 , Page(s): 263 - 266
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (266 KB) |  | HTML iconHTML  

    This paper presents new experimental results about the error correction performance of an iterative threshold decoder at relatively high signal to noise ratio. To accomplish this task, an accelerated characterization platform has been developed. Without this platform, it would take approximately 37.23 years in computational time with a software version of the decoder to get the error correction performances over an extended signal to noise range. An acceleration factor of 4812 is obtained by using the accelerated characterization platform. The platform constitutes a new way for characterizing quickly and efficiently a new error correction algorithm. The acceleration characterization platform has allowed verifying the error correction performance at high SNR which will require a prohibitive computational time on a conventional computer. View full abstract»

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  • Multiplexer-based binary incrementer/decrementers

    Publication Year: 2005 , Page(s): 219 - 222
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (148 KB) |  | HTML iconHTML  

    In this paper, novel multiplexer (MUX)-based incrementer/decrementers are proposed. The proposed designs are more efficient in terms of speed and hardware complexity compared to the adder-based ones for both signed and unsigned cases. A FPGA implementation comparison shows that the proposed design reduces both area and delay close to 40%. The power consumed by the MUX-based design is almost 35% less than that of the carry propagation adder (CPA)-based design. View full abstract»

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  • Linearity enhancement in a configurable sigma-delta modulator

    Publication Year: 2005 , Page(s): 59 - 62
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (399 KB) |  | HTML iconHTML  

    A highly linear sigma-delta modulator for dual-standard receivers is presented. The modulator makes use of low-distortion sigma-delta modulator architecture to attain high linearity over a wide bandwidth. The dual-band modulator employs a 2nd order single-bit sigma-delta modulator with feedforward path for GSM mode and a 4th order modified cascaded modulator with single-bit in the first stage and 4-bit in the second for WCDMA mode. The modulator is designed in TSMC 0.18μm CMOS technology and operates at 1.8 supply voltage. It achieves in GSM/WCDMA mode a peak SNDR of 83/75dB, a 96/84dB SFDR and an IMD3 of -93/-82dB for an OSR of 160/16. View full abstract»

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  • Optimized distributed processing of scaling factor in CORDIC

    Publication Year: 2005 , Page(s): 35 - 38
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (272 KB) |  | HTML iconHTML  

    CORDIC is a well known iterative algorithm used to evaluate various transcendental functions. There have been a number of papers describing various ways of speeding up this algorithm. One of the performance bottlenecks of CORDIC is the requirement to multiply the results of the x and y data path by a constant scaling factor. Depending on the architecture, such solutions might not necessarily provide added benefits. In this paper, processing of the scaling factor is applied in a distributed way in order to achieve maximum efficiency for both pipelined and recursive architectures. View full abstract»

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  • Multipath greedy algorithm for canonical representation of numbers in the double base number system

    Publication Year: 2005 , Page(s): 39 - 42
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (261 KB) |  | HTML iconHTML  

    The double base number system (DBNS) has been used in applications such as cryptography and digital filters. Two important properties of this type of representation are high redundancy and sparseness, which are key in eliminating carry propagation in basic arithmetic operations. High redundancy poses challenges in determining the canonical double base number representation (CDBNR) of an algebraic value. An exhaustive search for this representation can be computationally intensive, even for relatively small values. The greedy algorithm is very fast and simple to implement, but only allows for a single near canonical double base number representation (NCDBNR). The multipath greedy (MG) algorithm discussed in this paper is much faster than exhaustive search and gives better performance since it dramatically increases the likelihood of finding canonical representations. Since multiple starting points are used, this algorithm is able to find more than one NCDBNR in a single run. View full abstract»

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  • Minimization of delay sensitivity to process induced voltage threshold variations

    Publication Year: 2005 , Page(s): 171 - 174
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (168 KB) |  | HTML iconHTML  

    Threshold voltage variations, resulting from underlying process variations, cause variations in circuit delay that can affect the chip timing yield. We study design techniques and optimization strategies that minimize the effects of threshold voltage variations on circuit delay variability. Specifically, we compare different static circuits (classic CMOS, ratioed logic, and transmission gate logic) and dynamic circuits and evaluate their limitations and benefits in terms of delay variability, performance penalty and area overhead. Based on our findings, we also introduce circuit design guidelines and techniques that help mitigate the effects of threshold voltage variations. By reducing delay variability on a per-gate basis, we show how one can build threshold voltage variations-aware gate libraries for use in deep submicron design. View full abstract»

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  • Distortion in RF CMOS short channel low noise amplifiers

    Publication Year: 2005 , Page(s): 369 - 372
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (441 KB) |  | HTML iconHTML  

    An approach to estimate the distortion in CMOS short-channel (0.18 μm gate length) RF low noise amplifiers (LNA), based on Volterra's series, is presented. Compact and accurate frequency-dependent closed form expressions describing the effects of the different transistor parameters on harmonic distortion are derived. For the first time, the second order distortion (HD2), which is crucial in homodyne receivers, is studied. The analytical analysis is verified through simulations and measured results of a 0.18 μm CMOS 5.8GHz folded-cascode LNA prototype chip geared towards sub-IV operation. Distortion-aware design guidelines for RF CMOS LNA's are provided throughout the paper. View full abstract»

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  • An alternate approach to modular multiplication for finite fields [GF (2m)] using Itoh Tsujii algorithm

    Publication Year: 2005 , Page(s): 103 - 105
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (238 KB) |  | HTML iconHTML  

    Modular arithmetic operations especially modular multiplication have extensive applications in elliptic curve cryptanalysis, error control coding and linear recurring sequences. These operations have steadily grown in the word size in the past. Current designs and approaches may not be the most efficient for such high word sizes. Also usually, most approaches optimize for either area or speed, not both. In this paper, we examine certain properties and elucidate certain alternative strategies of and on the Itoh Tsujii algorithm (Guajardo and Paar, 2002) that will make it suitable for this emerging scenario. These strategies take a holistic approach to the problem, and aims at optimizing both speed and area for a given word length. These claims are supported by mathematical analysis, simulation and synthesis of a prototype of the suggested strategy. We also examine various enhancements that can be effected in the given architecture. View full abstract»

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  • A high precision and linearity differential capacitive sensor circuit dedicated to bioparticles detection

    Publication Year: 2005 , Page(s): 299 - 302
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (260 KB) |  | HTML iconHTML  

    The authors presented in this paper an accurate and simple topology circuit dedicated to measure very small percentage of differential capacitance variations. The proposed circuit is based on a charge-based capacitance measurement method (CBCM). The simplified architecture and measurement linearity of the proposed circuit are the two main advantages required to satisfy the design criteria of capacitive sensors array intended for bio-particles detection. The presented simulation results give a minimum measurable differential capacitance of 7 aF in a linearity for 10 fF variation instead of a minimum level of 10 aF in 2 fF variation reported by very recent literature. View full abstract»

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  • A 130nm partially depleted SOI technology menu for low-power applications

    Publication Year: 2005 , Page(s): 175 - 178
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (330 KB) |  | HTML iconHTML  

    In this paper, we present a technology-based menu where the target performance and power consumption are achieved by selecting a given design point (supply voltage, normal VT, low VT and DTMOS transistors) according to a given application. Through analyses made at synthesis and silicon measurements levels, it is shown that the best results are obtained by optimizing the SOI technology for the targeted power supply voltage. At the nominal 1.2V supply voltage, this is achieved by setting a higher threshold voltage VT to limit the cut-off currents. The power gains are in the order of 25% to 30% for the same performance. To further reduce the power dissipation, targeting the ultra-low-voltage range (0.5V) is very attractive when performance is not an issue. Using low-VT SOI transistors allows significant gains in terms of speed and power. The power-delay product of a 16-bit multiplier is improved by a 2.4 factor. View full abstract»

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  • A fully reconfigurable controller dedicated to implantable recording devices

    Publication Year: 2005 , Page(s): 303 - 306
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (220 KB) |  | HTML iconHTML  

    Neural signals monitoring systems become a key issue to cortical bioelectrical comprehension research. This paper describes the implementation of a dynamically reconfigurable controller dedicated for real-time implantable acquisition systems. The authors presented the cortical signal's characteristics and the requirements needed to extract and reconstruct the signal once transmitted outside the implant. The implementation of a wavelet transformation used as a feature extraction for spike detection, compression and denoising techniques were reported. A packet based protocol permitted to communicate in both directions with the implant trough the wireless link. A complete 32 channels prototype based on an optimized pipelined architecture was implemented and the resources' usage for further expansion was discussed. View full abstract»

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  • An FPGA implementation of an OFDM adaptive modulation system

    Publication Year: 2005 , Page(s): 353 - 356
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (179 KB) |  | HTML iconHTML  

    This paper investigates the hardware and architecture requirements for an OFDM adaptive modulation system. The hardware modules for a baseband adaptive uncoded OFDM transmitter, receiver and feedback link have been implemented on an FPGA. This system is used for fast hardware-in-the-loop simulation when combined with the implementation of a wireless channel model. It is also demonstrated that one high-end FPGA chip can provide all the resources necessary for the implementation of the system. View full abstract»

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  • Comparisons of different approaches of realizing IP block configuration in SystemC

    Publication Year: 2005 , Page(s): 83 - 86
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (184 KB) |  | HTML iconHTML  

    SystemC is a quasi open source event driven HDL (hardware description language) reference simulator which was introduced in September 1999 from the OSCI. At first, it meant to be a replacement for VHDL, and, although SystemC can be use for RTL modeling, it is now envisioned by the community as a high level system simulator. SystemC inherits all the properties, methodologies and mechanics of its bases (C and C++) which can be seen as macro-assemblers. This has the positive effect of having a lot of freedom in manners of doing things. This freedom can be beneficial because a given methodology can be chosen accordingly and more appropriately to the situation. On the other hand, freedom has a cost and a designer or IP (intellectual property) provider can lose a lot of time trying to figure out which methodology best fit his needs. In this paper, we establish a comprehensive list of all the different mechanisms for configuring an IP in SystemC. We then compare the different methods and highlight the ones which would best suite, following our opinions, the IP development process and publishing cases. View full abstract»

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  • Hardware implementation of large number multiplication by FFT with modular arithmetic

    Publication Year: 2005 , Page(s): 267 - 270
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (278 KB) |  | HTML iconHTML  

    Modular multiplication (MM) for large integers is the foundation of most public-key cryptosystems, specifically RSA, El-Gamal and the elliptic curve cryptosystems. Thus MM algorithms have been studied widely and extensively. Most of works are based on the well known Montgomery multiplication method (MMM) and its variants, which require multiplication in N. Authors have always avoided the fast Fourier transform (FFT) method believing that it is impractical for present system sizes despite its smaller complexity order. In this paper, the authors presented the design and hardware implementation of a FFT-based algorithm using modular arithmetic to efficiently compute very large number multiplications. The algorithm has been implemented in CASM, an intermediate level HDL developed in the laboratory. The target architecture is a FPGA. The algorithm is scalable and can easily be mapped to any operand size. Results show that such algorithm implementation starts to be useful for 4096-bit operands and beyond. View full abstract»

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  • A systematic approach for design of broadband CMOS amplifiers

    Publication Year: 2005 , Page(s): 251 - 254
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (486 KB) |  | HTML iconHTML  

    This article presents a novel method for the design of broadband amplifiers in CMOS technology. The proposed design is based on equalizing the frequency response of NMOS transistors over the amplifier bandwidth. The compensating network is realized using passive elements available in CMOS technology. Simulation results indicate successful implementations of broadband amplifiers in 0.18 μm CMOS with the bandwidth up to 30 GHz. The paper also reviews the design of broadband matching networks of the amplifier, completing the design process of broadband CMOS amplifiers. View full abstract»

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  • High-speed differential frequency-to-voltage converter

    Publication Year: 2005 , Page(s): 373 - 376
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (180 KB) |  | HTML iconHTML  

    This paper proposes a high-speed integrating frequency-to-voltage converter. It overcomes the deficiencies of previous converters by removing 2 of their main bottlenecks: event sequencing using pulses and the use of full-swing signals. By using a single-phase algorithm and circuit-level improvements a frequency-to-voltage converter can operate up to 5 GHz and is able to discriminate between signals whose periods differ by as little as 0.5ps. View full abstract»

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  • System integration of high voltage electrostatic MEMS actuators

    Publication Year: 2005 , Page(s): 155 - 158
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (321 KB) |  | HTML iconHTML  

    A system integration for high voltage (HV) electrostatic microelectromechanical systems (MEMS) actuators is introduced on a micro-printed circuit board (PCB). The system includes a programmable microcontroller, a programmable DC/DC converter, a multi output HV interface and electrostatic MEMS actuators. The system produces high output voltages (10-300V) and can control a large variety of MEMS capacitive loads (1 to 50pF) by combining diverse technologies. This system proves that technologies, such as low voltage CMOS of different processes, high voltage DMOS and MEMS, can interact, communicate and even be integrated as a system in package (SIP), providing significant size and cost reductions. View full abstract»

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  • A 1 V low-power low-noise DTMOS based class AB opamp

    Publication Year: 2005 , Page(s): 307 - 310
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (785 KB) |  | HTML iconHTML  

    In this paper, the authors described a novel class AB opamp based on dynamic threshold voltage transistors (DTMOS) for low voltage (1-V), low power and low noise applications. The opamp is used to build the front-end receiver part of a near infrared spectroreflectometry (NIRS) device. The opamp has a two-stage configuration; DTMOS pseudo pMOS differential input pairs are used for input common-mode range enhancement, followed by a single ended class AB output. Experimental measurements from previous designs confirm the usage of a DTMOS device to build a 1-V opamp, using standard 0.18-μm CMOS technology. The performed post-layout simulation results show an input referred noise of 107 nV/√Hz at 1 kHz, and a power consumption of 33.1 μW under 5 pF and 10 kΩ loads. The dc open loop gain is 60 dB, and a unity frequency of 2.73 MHz. The opamp has a CMRR of 100 dB, and input and output swings of 0.6 V and 0.8 V respectively. View full abstract»

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  • On the effect of clock jitter in IF and RF direct sampling systems

    Publication Year: 2005 , Page(s): 63 - 66
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (154 KB) |  | HTML iconHTML  

    The effect of clock jitter on sampling systems is presented. Analytical expressions are derived for the signal-to-noise ratio using the autocorrelation function and its properties. Special focus is given to direct sampling systems for signals with raised cosine power spectral density. Phase noise requirements in CDMA systems are calculated with respect to SNR. View full abstract»

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  • Wavelet-domain image denoising algorithm using series expansion of coefficient P.D.F. in terms of Hermite polynomials

    Publication Year: 2005 , Page(s): 271 - 274
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (437 KB) |  | HTML iconHTML  

    A new wavelet-domain image denoising algorithm is proposed that uses series expansion of continuous probability density function (pdf) for estimating wavelet coefficient variance field. The expanded pdf is derived using standard normal as weighting function that results the Hermite polynomials in the series. Variance field estimated using the proposed algorithm is used in a minimum mean square error (MMSE) estimator to restore the noisy image wavelet coefficients. Simulation results on standard images show improved performance both in visual quality and in terms of peak signal to noise ratio (PSNR) as compared to other recent image denoising methods. View full abstract»

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  • Java-enabled low cost RF vector network analyzer

    Publication Year: 2005 , Page(s): 377 - 380
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (532 KB) |  | HTML iconHTML  

    This paper describes a compact, low cost, low power vector network analyzer. The instrument's measurement range spans from 300 kHz up to 1500 MHz. The design was conceived to make the instrument generic and suited for many application areas. The instrument runs a local Web server, hosting a Java applet that contains application specific data processing software. We present the system architecture, discuss sub-block performance and propose some possible applications. View full abstract»

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