An important aspect of memory design is to translate the logical block diagram into a chip plan of the actual placement in layout of the key higher level cells and how they will interact with each other. The first place to start is with the configuration of the memory cell array in rows and columns which in turn will determine the column decode and row decode scheme. In the case of a dual port there are 2 sets of column decoders and 2 sets of row decoders ? one for each port. The column decode must be chosen such that it selects the appropriate number of columns within the array that will result in the required bits per word (BPW) that the customer requires. This paper presents various array configurations and the relationship between the total bits, bits per word, number of rows and number of columns.