SRAM Design - Sensing Scheme

A good design approach is to first consider the read cycle by designing the read path from the memory cell all the way out to the Data Out Pad. This tutorial takes the small signal that the memory cell creates and focuses on the Sensing Scheme that is required to create the gain necessary to create a full CMOS level. The function and design of the Sense Amp will be discussed in detail as well as the key requirements of the various control signals. Some of which have dual purposes such as controlling precharge and performing a 1 of 2 decode. There are many subtle things that must be considered and analyzed when designing the Sensing Scheme, not only in the schematics but in the layout as well. As such, portions of the layout will be reviewed along with an approach that eliminates noise that could cause it to fail. Plots of the layout will be provided along with an extracted SPICE netlist. Waveforms from the SPICE simulation will also be reviewed.