Part 2 will expand the analysis of delay and fanout to include the additional parasitic capacitance load that occurs from layout. A standardized method for converting capacitance to equivalent gate size will be presented, and the examples from Part 1 will be reworked to include parasitic capacitance. It is imperative that there be a good understanding of how layout causes parasitic capacitance which can greatly affect the performance and functionality of a design. We will evaluate this by first reviewing the basics of layout with substantial focus on the metal interconnect layers and the types of capacitance the various structures create. Finally, a simulation methodology will be presented for incorporating the actual extracted layout into SPICE for an accurate analysis of the design.