This paper appears in:
Reliability Physics Symposium, 2008. IRPS 2008. IEEE International
Date of Conference:
April 27 2008-May 1 2008
Author(s):
Mielke, N.
Intel Corp., Santa Clara, CA
Marquart, T.
;
Ning Wu
;
Kessenich, J.
;
Belgal, H.
;
Schares, E.
;
Trivedi, F.
;
Goodness, E.
;
Nevill, L.R.
Page(s):
9 - 19
Product Type:
Conference Publications
Abstract
NAND flash memories have bit errors that are corrected by error-correction codes (ECC). We present raw error data from multi-level-cell devices from four manufacturers, identify the root-cause mechanisms, and estimate the resulting uncorrectable bit error rates (UBER). Write, retention, and read-disturb errors all contribute. Accurately estimating the UBER requires care in characterization to include all write errors, which are highly erratic, and guardbanding for variation in raw bit error rate. NAND UBER values can be much better than 10-15, but UBER is a strong function of program/erase cycling and subsequent retention time, so UBER specifications must be coupled with maximum specifications for these quantities.
Index Terms
Index Terms are available to subscribers and IEEE members.
On page(s): 9
Conference Location : Phoenix, AZ
E-ISBN : 978-1-4244-2050-6
Print ISBN: 978-1-4244-2049-0
INSPEC Accession Number: 10074274
Digital Object Identifier : 10.1109/RELPHY.2008.4558857
Date of Current Version :
09 July 2008
Issue Date :
April 27 2008-May 1 2008
Available to subscribers and IEEE members.
Available to subscribers and IEEE members.
