Abstract
PPV phase macromodels are important for speeding up simulation of oscillator related circuits, such as PLLs, without sacrificing accuracy. Prior numerical methods for extracting PPVs face very significant robustness and accuracy problems when confronted with digitally controlled oscillators (DCOs, core building blocks in digital phase-locked loops), due to large RC time-constants from gated capacitors. In this paper, we present a hierarchical harmonic balance based technique for numerically extracting the PPV of DCOs from their SPICE-level circuit descriptions. The proposed method applies hierarchical circuit partitioning and multi-level Newton methods to achieve dramatically superior convergence and PPV accuracy in the presence of large RC time-constants. We validate the method on a large DCO with many gated capacitors and demonstrate that it can extract the PPV efficiently and robustly, succeeding when prior methods fail. The method also provides speedups of an order of magnitude for large circuits, in addition to having significantly smaller memory requirements
