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Performance driven optimization of network length in physical placement

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3 Author(s)
Donath, Wilm ; IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA ; Kudva, P. ; Reddy, L.

A novel technique to significantly improve the performance of a design by the movement of sets of gates during or after timing driven placement is proposed. A method to identify optimal set of circuit (gate) movements to enhance timing is presented. Experimental results with a min-cut placement tool indicate that the proposed approach of direct manipulation of circuit locations, significantly improves the timing of large partitions of a chip

Published in:

Computer Design, 1999. (ICCD '99) International Conference on

Date of Conference:

1999