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This work proposes a 10-b two-stage DAC with an area-efficient multiple-output voltage selector and a linearity-enhanced DAC-embedded op-amp for LCD column driver ICs. The proposed voltage selector is divided into two stages, MSB and LSB decoders; this design requires fewer switches compared with tree-type voltage selectors, enabling a smaller die area. The proposed 6-b two-voltage selector occupies only 61% of the area needed for a 6-b tree-type two-voltage selector. This study also develops a generalized architecture for an area-efficient voltage selector for multiple outputs. To improve the linearity of the DAC-embedded op-amp, the differential pairs operate at the edge of the saturation region. The 10-b DAC prototypes were produced with 0.35- μm/0.5- μm CMOS technology with the worst DNL/INL being 0.44/0.58 LSB.
Date of Publication: June 2013