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Wafer handling during the manufacturing process introduces micro-cracks and flaws at the wafer edge. The aim of this work was to determine whether an initial crack would be able to propagate through the silicon active region of power devices when it is subjected to high electro-thermal loads during its application or during thermal cycling tests. We have determined the most critical crack propagation cases. These have been simulated using the ANSYS® FEA software and energy release rate G (ERR) has been calculated for different crack lengths, locations, or thermal loads, and then compared to the silicon critical ERR of the silicon. Temperature profiles that reproduce the typical device operation conditions are retrieved with electro-thermal simulation. Failure analysis performed on these power devices has revealed some typical propagation paths.