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This paper presents a digital background calibration technique that intentionally exploits process variation and noise in comparators to correct conversion errors caused by interstage gain error, gain nonlinearity, and capacitor mismatch in pipelined ADCs. The merits of this technique lies in its design simplicity, fast convergence speed, and low power. Simulation results are presented for a 12-bit pipelined ADC, similar to that described by Murmann and Boser , and Keane et al.,  using low-gain amplifiers. With calibration, the SNDR and SFDR are improved from 47 and 49 dB to 72 and 92 dB, respectively. The number of conversions required for convergence is 106, which is about 4 times faster than that of Keane et al. and 40 times faster than that of Murmann and Boser.