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Server-class DDR3 SDRAM memory buffer chip

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8 Author(s)
G. A. Van Huben ; IBM Systems and Technology Group, Poughkeepsie, NY, USA ; K. D. Lamb ; R. B. Tremaine ; B. E. Aleman
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IBM System i®, System p®, and System z® servers require an efficient ultrareliable high-performance memory subsystem. The fourth-generation IBM advanced memory buffer (AMB) chip provides industry-leading performance, scalability, and reliability for the double-data-rate 3 (DDR3) synchronous dynamic random access memory (SDRAM) subsystems employed across a wide range of server platforms. The new IBM AMB employs a cyclic redundancy code-protected packet-protocol-based 6.4-Gb/s host channel, as well as dual 9-byte/10-byte wide 800 to 1,333-Mb/s SDRAM interfaces with dynamic calibration for optimal signal integrity under varied device and system environmental conditions. Applications support industry-standard dual inline memory module (DIMM) and low-latency high-capacity proprietary DIMM packages in conventional multichannel and redundant array of independent memory system architectures. A fully configured daisy-chain topology contains up to 256 GB of memory per host channel. This paper describes the IBM AMB chip architecture, design, and key engineering aspects.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:56 ,  Issue: 1.2 )