By Topic

Distributed TSV Topology for 3-D Power-Supply Networks

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Healy, M.B. ; TJ Watson Res. Center, IBM Res., Yorktown Heights, NY, USA ; Sung Kyu Lim

3-D integration has the potential to increase performance and decrease energy consumption. However, there are many unsolved issues in the design of these systems. In this work we study the design of 3-D power supply networks and demonstrate a technique specific to 3-D systems that improves IR-drop and dynamic noise over a straightforward extension of traditional design techniques. Previous work in 3-D power delivery network design has simply extended 2-D techniques by treating through-silicon vias (TSVs) as extensions of the C4 bumps. By exploiting the smaller size and much higher interconnect density possible with TSVs we demonstrate significant reduction of nearly 50% in the IR-drop and 42% in the dynamic noise of our large-scale 3-D design. Simulations also show that a 3-tier stack with the distributed TSV topology actually lowers IR-drop by 21% and dynamic noise by 32% over a non-3-D system with less power dissipation. We analyze the power distribution network of an envisioned 1000-core processor with 30 stacked dies and show scaling trends related to both increased stacking and power distribution TSVs. Finally, we examine several techniques for minimizing IR-drop and dynamic noise and their effects on our large-scale 3-D system.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:20 ,  Issue: 11 )