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Leakage power has become the dominant factor to the total power consumption when technology scales down to nano-region. Moreover, due to the exponential relationship between leakage power and temperature, positive feedback loop can cause thermal-runaway hazard. This poses a significant barrier for 3D integration of multi-cache-core processor, which has high I/O bandwidth but also has high leakage-power density and long heat-removal path. Nano-Electro-Mechanical Switches (NEMS) are among the most promising emerging devices to solve the thermal-runaway problem due to their zero leakage current and infinite sub-threshold slope. In order to have a proper control of thermal-runaway hazard for many-core system, this paper studies hybrid CMOS-NEMS designs of thermal buffer and power gating to reduce leakage power and thermal-runaway at thermal-time-constant scale. Experimental results show that our proposed NEMS based thermal management can effectively prevent the thermal-runaway in 3D multi-cache-core processor.
Date of Conference: 8-9 June 2011