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A 1-Gb/s, four-state, sliding block Viterbi decoder

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2 Author(s)
Black, P.J. ; Dept. of Electr. Eng., Stanford Univ., Palo Alto, CA, USA ; Meng, Teresa H.‐Y.

To achieve unlimited concurrency and hence throughput in an area-efficient manner, a sliding block Viterbi decoder (SBVD) is implemented that combines the filtering characteristics of a sliding block decoder with the computational efficiency of the Viterbi algorithm. The SBVD approach reduces decode of a continuous input stream to decode of independent overlapping blocks, without constraining the encoding process. A systolic SBVD architecture is presented that combines forward and backward processing of the block interval. The architecture is demonstrated in a four-state, R=1/2, eight-level soft decision Viterbi decoder that has been designed and fabricated in double-metal CMOS. The 9.21 mm×8.77 mm chip containing 150 k transistors is fully functional at a clock rate of 83 MHz and dissipates 3.0 W under typical operating conditions (VDD=5.0 V, TA =27°C). This corresponds to a block decode rate of 83 MHz, equivalent to a decode rate of 1 Gb/s. For low-power operation, typical parts are fully functional at a clock rate of greater than 12 MHz, equivalent to a decode rate of 144 Mb/s, and dissipate 24 mW at VDD =1.5 V, demonstrating extremely low power consumption at such high rates

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:32 ,  Issue: 6 )

Date of Publication:

Jun 1997

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