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IBM POWER7 processor circuit design

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6 Author(s)
D. F. Wendel ; IBM Deutschland Research and Development GmbH, Boeblingen, Germany ; J. Barth ; D. M. Dreps ; S. Islam
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The IBM POWER7® processor contains many innovative circuit ideas that enable advanced architectural features. A high-density embedded dynamic random access memory is used to provide 32 MB of level-3 cache. Improved input/output (I/O) links provide up to 50 GB/s of I/O bandwidth. An innovative phase-locked loop design allows for dynamic, per-core frequency variation, and unique multiport techniques for register files as well as six-transistor cell-based memory cells to support the superscalar multithreaded out-of-order processor.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:55 ,  Issue: 3 )