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A 54-862-MHz single-chip CMOS transceiver with a single LC voltage-controlled oscillator (VCO) fractional-N synthesizer is developed for TV-band white-space communications and cognitive radio applications. The transceiver is based on a single-conversion zero-IF architecture with integrated harmonic filtering capability. A combined harmonic rejection mixer and coarse RF tracking filter significantly lessens the in-band harmonic emission problem in the transmitter, as well as the harmonic mixing problem in the receiver. A fractional-N phase-locked loop (PLL) with only a single LC VCO and a wideband multimodulus local oscillator (LO) generator seamlessly covers the entire band. A wideband semi-dynamic divide-by-1.5 circuit is adopted in the LO generator to reduce the VCO tuning range requirement by 25 %. A pseudoexponential capacitor bank structure in the LC VCO substantially reduces the KVCO and fstep variations across the total band, which is beneficial for maintaining the PLL loop stability and dynamics over the wide band. The transceiver is implemented in 0.18-μ m CMOS, and operates with a single 1.8-V supply. The transmitter delivers a nominal output power of -3 dBm, and exhibits OP1 dB of >; +6.4 dBm, OIP3 of >; +15.9 dBm, and error vector magnitude (EVM) of <; -34.7 dB for 64-QAM signal. The image and carrier leakage calibration circuits suppress the leakage components below -41 dBc across the entire band. The receiver achieves about 100-dB gain dynamic range, 3.5-6.9-dB noise figure, <; -29-dB EVM, and -43.4/-59.7-dBc third/fifth harmonic mixing suppression. The synthesizer and LO generator achieves the integrated phase noise <; 0.8 rms degree over the entire band.