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Devices incorporating high-speed digital receivers must tolerate timing instability. The ability of the receiver to correctly place a receive strobe within the data valid region of a bit fundamentally determines the bit error rate performance for a design or a particular device. The device must meet its performance requirements in the presence of non-ideal timing. Timing irregularities can be introduced from additive non-deterministic noise sources injecting random jitter (Rj); deterministic distortion such as a limited channel bandwidth injecting data dependent jitter (DDj) or circuit oscillations and coupled clocks injecting periodic jitter (Pj). For self-clocked SERDES interfaces, the device is further tasked with recovering correct timing from the irregular edges of the received data signal itself; there is no reference clock to provide the correct bit timing. Incoming bits are timed with a clock data recovery circuit (CDR.) SERDES devices are commonly targeted to meet performance budgets for tolerance of DDj, Rj and Pj. Further, the bandwwidth content of the Rj and Pj components are defined to be within specified frequency ranges. This paper presents the details of a working design to introduce calibrated timing instability for high-speed digital test signals up to 12.8Gbps, including component choices and use considerations. The design's independent programmed control for amplitude and frequency content of Pj and Rj and calibrated DDj will be presented. Each independent form of jitter can be injected to amplitudes and frequencies beyond that required of all the common SERDES standards. Bench instrument correlation results will be presented and device characterization experiences will be discussed.