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A 13MHz input, 480MHz output Fractional Phase Lock Loop (PLL), having 1MHz bandwidth, is presented here. To handle the non-integer feedback divider ratio (480/13), a novel approach is chosen. A Delay Lock Loop (DLL) is used to generate 13 phases of the 480MHz VCO clock; one of these phases is multiplexed to an integer mode feedback divider; every reference cycle the multiplexer shifts to the adjacent phase, resulting in the period of the feedback clock, after the divider, being 1/13th of a VCO clock period short of an integer multiple. This results in an effective fractional division. The Phase Detector (PD) does not see any phase errors due to this operation; hence no additional filtering is required in the loop. The loop bandwidth can therefore be maintained to a value as high as one tenth of the reference clock, in contrast to other popular fractional PLL schemes. The affect of the DLL to the PLL loop stability and jitter is analyzed and found to be non significant. The PLL can be re-configured to also support 15.36MHz and 16.8MHz in fractional mode, and 20MHz, 19.2MHz, 12MHz, 24MHz and 48MHz in integer mode, while always maintaining high bandwidth. The PLL is designed and simulated in 90nm CMOS. It occupies an area of 0.1 sq mm, and does not require off-chip components.