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Low-complexity high throughput VLSI architecture of soft-output ML MIMO detector

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3 Author(s)
Cupaiuolo, T. ; Adv. Syst. Technol., STMicrolectronics, Agrate Brianza, Italy ; Siti, M. ; Tomasoni, A.

In this paper a VLSI architecture of a high throughput and high performance soft-output (SO) MIMO detector (the recently presented Layered ORthogonal Lattice Detector, LORD) is presented. The baseline implementation includes optimal (i.e. maximum-likelihood - ML - in the max-log sense) SO generation. A reduced complexity variant of the SO generation stage is also described. To the best of the authors' knowledge, the proposed architecture is the first VLSI implementation of a max-log ML MIMO detector which includes QR decomposition and SO generation, having the latter a deterministic very high throughput thanks to a fully parallelizable structure, and parameterizability in terms of both the number of transmit and receive antennas, and the supported modulation orders. The two designs achieve a very high throughput making them particularly suitable for MIMO-OFDM systems like e.g. IEEE 802.11n WLANs: the most demanding requirements are satisfied at a reasonable cost of area and power consumption.

Published in:

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010

Date of Conference:

8-12 March 2010