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This paper investigates the design of a dual-rail precharge logic family whose power consumption is insensitive to unbalanced load conditions thus allowing adopting a semi-custom design flow (automatic place and route) without any constraint on the routing of the complementary wires. The proposed logic is based on a novel encoding concept where the information is represented in the time domain rather than in the spatial domain as in a standard dual-rail logic. In this work, a logic family which exploits the proposed concept has been implemented. Implementation details and simulation results are reported which show a power consumption independent of the sequence of processed data and routing capacitances. An improvement in the energy consumption balancing up to 50 times and an area reduction up to 60% with respect to the state of the art have been obtained.
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on (Volume:19 , Issue: 7 )
Date of Publication: July 2011