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In this paper a fully functional RFIC DVB-H receiver is presented. The paper discusses some of the important issues faced during the system design stage, such as sensitivity and linearity in a multi-band and multi-mode receiver coupled with demands for smaller die area and low power consumption. Design challenges in developing an RFIC chipset to receive real-time digital TV pictures are discussed including GSM co-location impact on handset design. A number of mitigations will be presented and validated in the form of a fully functional broadband direct-conversion receiver, which has been designed using a commercial 0.25 u BiCMOS process. The measured results of the receiver were very encouraging. Reasons for successful functionality of the chipset, meeting commercial requirements, from the first silicon are presented.