Skip to Main Content
Solving Sudoku puzzles is a mind-bending activity that many people enjoy during their spare time. As such, for those being acquainted with computers, it becomes an irresistible challenge to build a computing engine for Sudoku solving. Many Sudoku solvers have been developed recently, using advanced techniques and algorithms to speed-up the computation. In this paper, we describe a hardware design for an FPGA implementation of a Sudoku solver. Furthermore, we show the performance of the above design for solving puzzles of order N 3 to 15.