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The TU Delft sudoku solver on FPGA

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4 Author(s)
van der Bok, K. ; Comput. Eng., Delft Univ. of Technol., Delft, Netherlands ; Taouil, M. ; Afratis, P. ; Sourdis, I.

Solving Sudoku puzzles is a mind-bending activity that many people enjoy during their spare time. As such, for those being acquainted with computers, it becomes an irresistible challenge to build a computing engine for Sudoku solving. Many Sudoku solvers have been developed recently, using advanced techniques and algorithms to speed-up the computation. In this paper, we describe a hardware design for an FPGA implementation of a Sudoku solver. Furthermore, we show the performance of the above design for solving puzzles of order N 3 to 15.

Published in:

Field-Programmable Technology, 2009. FPT 2009. International Conference on

Date of Conference:

9-11 Dec. 2009