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Modeling Low-k Dielectric Breakdown to Determine Lifetime Requirements

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2 Author(s)
Bashir, M. ; Georgia Inst. of Technol., Atlanta, GA, USA ; Milor, L.

Low-k dielectric breakdown and stress migration have emerged as new sources of wearout for on-chip interconnect. This article analyzes statistical data from a 45-nm test chip and constructs a methodology to determine the lifetime of low-k materials under process variations.

Published in:

Design & Test of Computers, IEEE  (Volume:26 ,  Issue: 6 )

Date of Publication:

Nov.-Dec. 2009

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