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An Efficient Multimode Multiplier Supporting AES and Fundamental Operations of Public-Key Cryptosystems

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3 Author(s)
Chen-Hsing Wang ; Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan ; Chieh-Lin Chuang ; Cheng-Wen Wu

This paper presents a highly efficient multimode multiplier supporting prime field, namely, polynomial field, and matrix-vector multiplications based on an asymmetric word-based Montgomery multiplication (MM) algorithm. The proposed multimode 128 ?? 32 b multiplier provides throughput rates of 441 and 511 Mb/s for 256-b operands over GF(P) and GF(2n) at a clock rate of 100 MHz, respectively. With 21 930 additional gates for Advanced Encryption Standard (AES), the multiplier is extended to provide 1.28-, 1.06-, and 0.91-Gb/s throughput rates for 128-, 192-, and 256-b keys, respectively. The comparison result shows that the proposed integration architecture outperforms others in terms of performance and efficiency for both AES and MM that is essential in most public-key cryptosystems.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:18 ,  Issue: 4 )

Date of Publication:

April 2010

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