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In this contribution a methodology is presented which allows the estimation of a system level ESD robustness from the ESD characterization on device level. The basic idea behind this methodology is that predominantly three different failure mechanisms exist. CDM-type stress (pulse duration ~1 ns) causes break down of dielectrics, e.g., gate oxides. The relevant parameter is the peak current of the discharge. Stress similar to HBM (time domain 50-200 ns) results usually in thermal damages due to the dissipated energy in the device. EOS damage (stress duration > 1 mus) are caused by thermal power forced into the device which itself is in thermal equilibrium. Examples are given where the ESD threshold voltage of system level tests on devices could be derived from the device characterization with an accuracy of 20-30 %.