By Topic

Parameter space exploration for robust and high-performance n-channel and p-channel symmetric double-gate FinFETs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Tawfik, S.A. ; Dept. of Electr. & Comput. Eng., Univ. of Wisconsin-Madison, Madison, WI, USA ; Kursun, V.

The influence of different device parameters on the electrical characteristics of n-channel and p-channel symmetric double-gate FinFETs is studied in this paper. Guidelines for enhancing the performance and suppressing the leakage currents are provided. A sub-threshold slope lower than 100 mV is achieved at the room temperature with fins thinner than half the gate length in a 32 nm FinFET technology. The maximum on-current to leakage current ratio of n-channel FinFETs at room temperature is achieved when the fin thickness and the gate-oxide thickness are 8 nm and 1.6 nm, respectively. Alternatively, the on-current to leakage currents ratio of p-channel FinFETs is maximized when the fin thickness and the gate-oxide thickness are 8 nm and 1.2 nm, respectively.

Published in:

Quality Electronic Design, 2009. ASQED 2009. 1st Asia Symposium on

Date of Conference:

15-16 July 2009