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Optimizing data flow graphs to minimize hardware implementation

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5 Author(s)
Gomez-Prado, D. ; ECE Dept., Univ. of Massachusetts, Amherst, MA ; Ren, Q. ; Ciesielski, M. ; Guillot, J.
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This paper describes an efficient graph-based method to optimize data-flow expressions for best hardware implementation. The method is based on factorization, common subexpression elimination (CSE) and decomposition of algebraic expressions performed on a canonical representation, Taylor Expansion Diagram. The method is generic, applicable to arbitrary algebraic expressions and does not require specific knowledge of the application domain. Experimental results show that the DFGs generated from such optimized expressions are better suited for high level synthesis, and the final, scheduled implementations are characterized, on average, by 15.5% lower latency and 7.6% better area than those obtained using traditional CSE and algebraic decomposition.

Published in:

Design, Automation & Test in Europe Conference & Exhibition, 2009. DATE '09.

Date of Conference:

20-24 April 2009