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A micropower CMOS algorithmic A/D/A converter

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1 Author(s)
Cauwenberghs, G. ; Dept. of Electr. & Comput. Eng., Johns Hopkins Univ., Baltimore, MD, USA

A low-power and compact VLSI architecture, implementing a bidirectional bit-serial A/D/A (analog-to-digital and digital-to-analog) converter, is presented. Both functions of algorithmic D/A conversion and successive approximation A/D conversion are combined into a single device, converting bits in the order from most to least significant. The MSB-first order guarantees robust implementation, relatively insensitive to component mismatches, offsets and nonlinearities. Also, since the A/D conversion makes use of the intermediate D/A conversion results, matched monotonic characteristics are obtained in both directions of conversion. The final D/A result is available at the end of A/D conversion, and can be used directly in applications calling for analog quantization. More general use of the A/D/A converter allows for bidirectional read/write digital access to local analog information in VLSI. The robust architecture supports dense integration of multiple low-power data conversion units along with digital processors or sensory circuitry in a standard CMOS process. Minimum sizing of active and passive devices in the implementation, to obtain optimal area and energy efficiency, is limited by clock feedthrough and finite gain considerations rather than matching requirements. Experimental results from a prototype VLSI implementation are given. Including control logic, the A/D/A cell measures 216 μm×315 μm in a 2-μm CMOS process, and achieves 8-b untrimmed monotonicity at 200 μW power consumption for a 20 μs conversion cycle. This corresponds to 4 nJ of energy dissipated per 8-b converted sample

Published in:

Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on  (Volume:42 ,  Issue: 11 )

Date of Publication:

Nov 1995

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