Skip to Main Content
With each technology node shrink, a silicon chip becomes more susceptible to soft errors. The susceptibility further increases as the voltage is scaled down to save energy. Based on analysis on cells from commercial libraries, we have quantified the increase in the soft error probability across 65 nm and 45 nm technology nodes at different supply voltages using the Qcrit based simulation methodology. The Qcrit for both bit cells and latches decreases by ~30% as the designs are scaled from 65 nm to 45 nm. This decrease is expected to continue with further technology scaling as well. The results show that at nominal voltage, the Qcrit for a latch is just ~20% more than that of the bit cell in sub-65nm technology nodes. Further, as the voltage is scaled from 1 V to 0.4 V, Qcrit decreases by ~5X which substantially increases the probability of an upset if a particle strike happens. This work shows that in sub-65 nm technology nodes with aggressive voltage scaling, it is equally critical to solve the soft error problems in logic (latches, flip-flops) as it is in SRAMs.