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Using Hardware Memory Protection to Build a High-Performance, Strongly-Atomic Hybrid Transactional Memory

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3 Author(s)
Baugh, L. ; Dept. of Comput. Sci., Illinois Univ., Urbana, IL ; Neelakantam, N. ; Zilles, C.

We demonstrate how fine-grained memory protection can be used in support of transactional memory systems: first showing how a software transactional memory system (STM) can be made strongly atomic by using memory protection on transactionally-held state, then showing how such a strongly-atomic STM can be used with a bounded hardware TM system to build a hybrid TM system in which zero-overhead hardware transactions may safely run concurrently with potentially-conflicting software transactions. We experimentally demonstrate how this hybrid TM organization avoids the common-case overheads associated with previous hybrid TM proposals, achieving performance rivaling an unbounded HTM system without the hardware complexity of ensuring completion of arbitrary transactions in hardware. As part of our findings, we identify key policies regarding contention management within and across the hardware and software TM components that are key to achieving robust performance with a hybrid TM.

Published in:

Computer Architecture, 2008. ISCA '08. 35th International Symposium on

Date of Conference:

21-25 June 2008

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