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Low-voltage green transistor using ultra shallow junction and hetero-tunneling

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7 Author(s)
Bowonder, A. ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA ; Patel, P. ; Kanghoon Jeon ; Jungwoo Oh
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A novel hetero-tunnel transistor (HtFET) with a heterostructure and ultra shallow junction parallel to the dielectric interface is proposed for low-voltage (low-power) electronics. Its potential of scaling Vdd down to 0.2 V is examined with quantum mechanical tunneling theory. Data from high-K metal-gate, Si on Ge hetero-tunnel transistor verifies the HtFET concept.

Published in:

Junction Technology, 2008. IWJT '08. Extended Abstracts - 2008 8th International workshop on

Date of Conference:

15-16 May 2008