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The nonuniform substrate thermal profile and process variations are two major concerns in the present-day ultra-deep submicrometer designs. To correctly predict performance/ leakage/reliability measures and address any yield losses during the early stages of design phases, it is desirable to have a reliable thermal estimation of the chip. However, the leakage power sources vary greatly due to process variations and temperature, which result in significant variations in the hotspot and thermal profile formation in very large scale integration chips. Traditionally, no leakage variations have been considered during full-chip thermal analysis. In this paper, the dependence behavior among the process variability, leakage power consumption, and thermal profile construction are established to effectively extract a reliable statistical thermal profile over a die at the microarchitectural level. Knowledge of this is the key to the design and analysis of circuits. The probability density functions of temperatures are extracted while considering the leakage variations due to the gate-length and oxide-thickness variations and while accounting for the coupling between the temperature and the total leakage. Two applications of the developed analyzer are investigated, namely, the evaluation of the hotspots' relocations and the total full-chip power estimation. Finally, the accuracy and efficiency of the developed analyzer are validated by comparisons with Monte Carlo simulations.