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This paper presents a unique on-chip digital control crystal oscillator (DCXO) module that is used for clock synchronization in MPEG2 data transport system. This module is built inside a phase-locked loop (PLL) and is achieved through flying-adder frequency synthesis architecture. It is designed at 27 MHz with a tuning range of plusmn10 kHz. The linearity at the range of 27 MHz plusmn10 kHz is measured as 0.001%. The frequency resolution is 1.6 Hz. This DCXO and its associated PLL consume 10 mW and occupies 0.15 mm2 in a 90-nm CMOS process. The contribution of this work is that this built-in DCXO can completely eliminate the need of external voltage-control crystal oscillator (VCXO) chip or on-chip VCXO block in MPEG2 clock synchronization and thus significantly reduces the system cost. This module has been used in a real HDTV SoC chip.
Circuits and Systems I: Regular Papers, IEEE Transactions on (Volume:55 , Issue: 8 )
Date of Publication: Sept. 2008