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Interconnection network switch architectures and combining strategies

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2 Author(s)
Dickey, S. ; Courant Inst. of Math. Sci., New York, NY ; Yue-Sheng Liu

We have studied a variety of switch architectures for use in the multistage interconnection network of a shared memory multiprocessor. In this paper, we investigate two techniques for improving network performance in the presence of contention: the use of multiple handshaking signals and the use of message combining. Simulation results are provided for implementation alternatives using switches of varying capabilities, in order to compare the effectiveness of different methods. We show that a practical combining switch design, the two-and-a-half-way combining switch, provides performance equivalent to that of other more expensive designs for systems with up to 1024 PEs

Published in:

Parallel Processing Symposium, 1994. Proceedings., Eighth International

Date of Conference:

26-29 Apr 1994