By Topic

A syntax-directed translation for the synthesis of delay-insensitive circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
S. C. Leung ; Dept. of Comput. Sci., Concordia Univ., Montreal, Que., Canada ; H. F. Li

A syntax-directed translation procedure for the synthesis of delay-insensitive circuits from graph-theoretic specifications is presented. No isochronic fork assumption is required for the correct operation of the synthesized circuits. The synthesized circuits are different from those obtained from Ebergen's synthesis method. In Ebergen's circuits, the voltage levels of a set of wires are used to encode which input events are most recently received. Special circuit elements (the N-element or the RCEL element) and two-phase to four-phase converters are needed to change the voltage levels of the encoding wires when input events are received. In the circuits obtained from the method in this paper, the wires encoding which input events are most recently received are the outputs of the toggles. When input events are received, they are sent directly or via demultiplexers to the toggles to change the voltage levels at their outputs. Two-phase to four-phase converters are not needed. The synthesis method is compared with Ebergen's synthesis method.<>

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:2 ,  Issue: 2 )