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A switch-memory chip for packet switching at gigabits per second

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1 Author(s)
H. Kanakia ; AT&T Bell Labs., Murray Hill, NJ, USA

The performance of store-and-forward packet switches is limited by access speeds of memory components used in the switch. Although the memory technology continues to improve, the memory bandwidth is expected to remain the bottleneck as networks move to the multi-gigabit range. The switch architecture described here offers a novel solution to this problem. The key component of the architecture is a CMOS VLSI chip named Switch Memory. By restricting high-speed data movements within the chip boundary, the Switch Memory chip provides gigabit switching. A prototype chip has been built and successfully tested. The chip forms a building block for a 14×14 packet switch, named Yswitch, with the total capacity of 14 Gigabits/sec

Published in:

VLSI Design, 1994., Proceedings of the Seventh International Conference on

Date of Conference:

5-8 Jan 1994