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An 8-bit 800- \mu\hbox {W} 1.23-MS/s Successive Approximation ADC in SOI CMOS

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2 Author(s)
Culurciello, E. ; Dept. of Electr. Eng., Yale Univ., New Haven, CT ; Andreou, A.G.

We report on an 8-bit successive approximation analog-to-digital converter (SA-ADC) that was designed and fabricated in 0.5-mum silicon on sapphire CMOS technology. The SA-ADC is capable of 32-MHz operation, providing 1.23-MS/s conversion rates, and consumes 800 muW at 3.3-V supply. The lack of substrate parasitic capacitances enables the use of small-area capacitors and reduces the noise coupling to the analog nodes. The circuits employ MOS transistors of different thresholds to optimize the performance and power dissipation of the system

Published in:

Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:53 ,  Issue: 9 )

Date of Publication:

Sept. 2006

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