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This paper describes the design of a four-valued memory cell based on a three-peak MOS-NDR circuit. We connect three MOS-NDR devices in parallel that can create a three-peak current-voltage curve by suitably arranging the parameters. Due to its folding I-V characteristics, multiple-peak NDR device is a very promising device for multiple-valued logic application. This memory cell structure can be easily extended to implement more states in a memory circuit.