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Four-valued memory circuit designed by multiple-peak MOS-NDR devices and circuits

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10 Author(s)
Dong-Shong Liang ; Dept. of Electron. Eng., Kun Shan Univ. of Technol., Taiwan ; Kwang-Jow Gan ; Long-Xian Su ; Chi-Pin Chen
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This paper describes the design of a four-valued memory cell based on a three-peak MOS-NDR circuit. We connect three MOS-NDR devices in parallel that can create a three-peak current-voltage curve by suitably arranging the parameters. Due to its folding I-V characteristics, multiple-peak NDR device is a very promising device for multiple-valued logic application. This memory cell structure can be easily extended to implement more states in a memory circuit.

Published in:

System-on-Chip for Real-Time Applications, 2005. Proceedings. Fifth International Workshop on

Date of Conference:

20-24 July 2005

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